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* signed divisions with constants are always done without idiv
git-svn-id: trunk@1965 -
This commit is contained in:
florian
parent
5ea49bedd0
commit
3582108be1
@ -61,110 +61,200 @@ implementation
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TI386MODDIVNODE
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*****************************************************************************}
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procedure ti386moddivnode.pass_2;
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function log2(i : dword) : dword;
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begin
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result:=0;
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i:=i shr 1;
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while i<>0 do
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begin
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i:=i shr 1;
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inc(result);
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end;
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end;
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var hreg1,hreg2:Tregister;
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power:longint;
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hl:Tasmlabel;
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op:Tasmop;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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procedure ti386moddivnode.pass_2;
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var
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hreg1,hreg2:Tregister;
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power:longint;
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hl:Tasmlabel;
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op:Tasmop;
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e : longint;
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d,l,s,m,a : dword;
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m_low,m_high,j,k : qword;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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if is_64bitint(resulttype.def) then
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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{ put numerator in register }
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location_reset(location,LOC_REGISTER,OS_INT);
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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if is_64bitint(resulttype.def) then
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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{ put numerator in register }
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location_reset(location,LOC_REGISTER,OS_INT);
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resulttype.def) Then
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begin
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if (aktOptProcessor <> class386) and
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not(cs_littlesize in aktglobalswitches) then
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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begin
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,S_L,31,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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emit_const_reg(A_AND,S_L,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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{ do the shift }
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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else
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begin
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{ a jump, but less operations }
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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objectlibrary.getjumplabel(hl);
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cg.a_jmp_flags(exprasmlist,F_NS,hl);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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end
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else
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emit_const_reg(A_SHR,S_L,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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cg.getcpuregister(exprasmlist,NR_EAX);
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emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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cg.getcpuregister(exprasmlist,NR_EDX);
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{Sign extension depends on the left type.}
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if torddef(left.resulttype.def).typ=u32bit then
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emit_reg_reg(A_XOR,S_L,NR_EDX,NR_EDX)
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else
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emit_none(A_CDQ,S_NO);
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if (nodetype=divn) and (right.nodetype=ordconstn) then
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begin
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if ispowerof2(tordconstnode(right).value,power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resulttype.def) Then
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begin
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if (aktOptProcessor <> class386) and
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not(cs_littlesize in aktglobalswitches) then
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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begin
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,S_L,31,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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emit_const_reg(A_AND,S_L,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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{ do the shift }
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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else
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begin
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{ a jump, but less operations }
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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objectlibrary.getjumplabel(hl);
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cg.a_jmp_flags(exprasmlist,F_NS,hl);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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end
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else
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emit_const_reg(A_SHR,S_L,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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e:=tordconstnode(right).value;
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d:=abs(e);
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{ Determine algorithm (a), multiplier (m), and shift factor (s) for 32-bit
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signed integer division. Based on: Granlund, T.; Montgomery, P.L.:
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"Division by Invariant Integers using Multiplication". SIGPLAN Notices,
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Vol. 29, June 1994, page 61.
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}
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{Division depends on the right type.}
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if Torddef(right.resulttype.def).typ=u32bit then
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op:=A_DIV
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else
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op:=A_IDIV;
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l:=log2(d);
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j:=qword($80000000) mod qword(d);
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k:=(qword(1) shl (32+l)) div (qword($80000000-j));
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m_low:=((qword(1)) shl (32+l)) div d;
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m_high:=(((qword(1)) shl (32+l)) + k) div d;
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while ((m_low shr 1) < (m_high shr 1)) and (l > 0) do
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begin
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m_low:=m_low shr 1;
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m_high:=m_high shr 1;
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dec(l);
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end;
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m:=m_high;
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s:=l;
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if (m_high shr 31)<>0 then
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a:=1
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else
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a:=0;
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cg.getcpuregister(exprasmlist,NR_EAX);
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emit_const_reg(A_MOV,S_L,m,NR_EAX);
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cg.getcpuregister(exprasmlist,NR_EDX);
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emit_reg(A_IMUL,S_L,hreg1);
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emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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if a<>0 then
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begin
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emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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{
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printf ("; dividend: memory location or register other than EAX or EDX\n");
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printf ("\n");
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printf ("MOV EAX, 0%08LXh\n", m);
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printf ("IMUL dividend\n");
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printf ("MOV EAX, dividend\n");
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printf ("ADD EDX, EAX\n");
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if (s) printf ("SAR EDX, %d\n", s);
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printf ("SHR EAX, 31\n");
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printf ("ADD EDX, EAX\n");
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if (e < 0) printf ("NEG EDX\n");
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printf ("\n");
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printf ("; quotient now in EDX\n");
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}
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end;
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{
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printf ("; dividend: memory location of register other than EAX or EDX\n");
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printf ("\n");
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printf ("MOV EAX, 0%08LXh\n", m);
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printf ("IMUL dividend\n");
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printf ("MOV EAX, dividend\n");
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if (s) printf ("SAR EDX, %d\n", s);
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printf ("SHR EAX, 31\n");
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printf ("ADD EDX, EAX\n");
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if (e < 0) printf ("NEG EDX\n");
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printf ("\n");
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printf ("; quotient now in EDX\n");
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}
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if s<>0 then
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emit_const_reg(A_SAR,S_L,s,NR_EDX);
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emit_const_reg(A_SHR,S_L,31,NR_EAX);
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emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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if e<0 then
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emit_reg(A_NEG,S_L,NR_EDX);
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cg.ungetcpuregister(exprasmlist,NR_EDX);
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cg.ungetcpuregister(exprasmlist,NR_EAX);
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location.register:=cg.getintregister(exprasmlist,OS_INT);
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EDX,location.register)
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end;
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end
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else
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begin
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cg.getcpuregister(exprasmlist,NR_EAX);
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emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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cg.getcpuregister(exprasmlist,NR_EDX);
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{Sign extension depends on the left type.}
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if torddef(left.resulttype.def).typ=u32bit then
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emit_reg_reg(A_XOR,S_L,NR_EDX,NR_EDX)
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else
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emit_none(A_CDQ,S_NO);
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,S_L,right.location.reference)
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else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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emit_reg(op,S_L,right.location.register)
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else
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begin
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hreg1:=cg.getintregister(exprasmlist,right.location.size);
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cg.a_load_loc_reg(exprasmlist,OS_32,right.location,hreg1);
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emit_reg(op,S_L,hreg1);
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end;
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{Division depends on the right type.}
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if Torddef(right.resulttype.def).typ=u32bit then
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op:=A_DIV
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else
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op:=A_IDIV;
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{Copy the result into a new register. Release EAX & EDX.}
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cg.ungetcpuregister(exprasmlist,NR_EDX);
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cg.ungetcpuregister(exprasmlist,NR_EAX);
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location.register:=cg.getintregister(exprasmlist,OS_INT);
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if nodetype=divn then
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EAX,location.register)
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else
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EDX,location.register);
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end;
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end;
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,S_L,right.location.reference)
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else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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emit_reg(op,S_L,right.location.register)
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else
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begin
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hreg1:=cg.getintregister(exprasmlist,right.location.size);
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cg.a_load_loc_reg(exprasmlist,OS_32,right.location,hreg1);
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emit_reg(op,S_L,hreg1);
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end;
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{Copy the result into a new register. Release EAX & EDX.}
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cg.ungetcpuregister(exprasmlist,NR_EDX);
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cg.ungetcpuregister(exprasmlist,NR_EAX);
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location.register:=cg.getintregister(exprasmlist,OS_INT);
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if nodetype=divn then
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EAX,location.register)
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else
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EDX,location.register);
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end;
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end;
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{*****************************************************************************
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