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* signed divisions with constants are always done without idiv

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git-svn-id: trunk@1965 -
This commit is contained in:
florian 2005-12-15 22:36:48 +00:00
parent 5ea49bedd0
commit 3582108be1
1 changed files with 187 additions and 97 deletions
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100
compiler/i386/n386mat.pas
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@ -61,13 +61,27 @@ implementation
TI386MODDIVNODE
*****************************************************************************}
procedure ti386moddivnode.pass_2;
function log2(i : dword) : dword;
begin
result:=0;
i:=i shr 1;
while i<>0 do
begin
i:=i shr 1;
inc(result);
end;
end;
var hreg1,hreg2:Tregister;
procedure ti386moddivnode.pass_2;
var
hreg1,hreg2:Tregister;
power:longint;
hl:Tasmlabel;
op:Tasmop;
e : longint;
d,l,s,m,a : dword;
m_low,m_high,j,k : qword;
begin
secondpass(left);
if codegenerror then
@ -84,8 +98,9 @@ implementation
location_force_reg(exprasmlist,left.location,OS_INT,false);
hreg1:=left.location.register;
if (nodetype=divn) and (right.nodetype=ordconstn) and
ispowerof2(tordconstnode(right).value,power) then
if (nodetype=divn) and (right.nodetype=ordconstn) then
begin
if ispowerof2(tordconstnode(right).value,power) then
begin
{ for signed numbers, the numerator must be adjusted before the
shift instruction, but not wih unsigned numbers! Otherwise,
@ -127,6 +142,81 @@ implementation
emit_const_reg(A_SHR,S_L,power,hreg1);
location.register:=hreg1;
end
else
begin
e:=tordconstnode(right).value;
d:=abs(e);
{ Determine algorithm (a), multiplier (m), and shift factor (s) for 32-bit
signed integer division. Based on: Granlund, T.; Montgomery, P.L.:
"Division by Invariant Integers using Multiplication". SIGPLAN Notices,
Vol. 29, June 1994, page 61.
}
l:=log2(d);
j:=qword($80000000) mod qword(d);
k:=(qword(1) shl (32+l)) div (qword($80000000-j));
m_low:=((qword(1)) shl (32+l)) div d;
m_high:=(((qword(1)) shl (32+l)) + k) div d;
while ((m_low shr 1) < (m_high shr 1)) and (l > 0) do
begin
m_low:=m_low shr 1;
m_high:=m_high shr 1;
dec(l);
end;
m:=m_high;
s:=l;
if (m_high shr 31)<>0 then
a:=1
else
a:=0;
cg.getcpuregister(exprasmlist,NR_EAX);
emit_const_reg(A_MOV,S_L,m,NR_EAX);
cg.getcpuregister(exprasmlist,NR_EDX);
emit_reg(A_IMUL,S_L,hreg1);
emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
if a<>0 then
begin
emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
{
printf ("; dividend: memory location or register other than EAX or EDX\n");
printf ("\n");
printf ("MOV EAX, 0%08LXh\n", m);
printf ("IMUL dividend\n");
printf ("MOV EAX, dividend\n");
printf ("ADD EDX, EAX\n");
if (s) printf ("SAR EDX, %d\n", s);
printf ("SHR EAX, 31\n");
printf ("ADD EDX, EAX\n");
if (e < 0) printf ("NEG EDX\n");
printf ("\n");
printf ("; quotient now in EDX\n");
}
end;
{
printf ("; dividend: memory location of register other than EAX or EDX\n");
printf ("\n");
printf ("MOV EAX, 0%08LXh\n", m);
printf ("IMUL dividend\n");
printf ("MOV EAX, dividend\n");
if (s) printf ("SAR EDX, %d\n", s);
printf ("SHR EAX, 31\n");
printf ("ADD EDX, EAX\n");
if (e < 0) printf ("NEG EDX\n");
printf ("\n");
printf ("; quotient now in EDX\n");
}
if s<>0 then
emit_const_reg(A_SAR,S_L,s,NR_EDX);
emit_const_reg(A_SHR,S_L,31,NR_EAX);
emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
if e<0 then
emit_reg(A_NEG,S_L,NR_EDX);
cg.ungetcpuregister(exprasmlist,NR_EDX);
cg.ungetcpuregister(exprasmlist,NR_EAX);
location.register:=cg.getintregister(exprasmlist,OS_INT);
cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EDX,location.register)
end;
end
else
begin
cg.getcpuregister(exprasmlist,NR_EAX);