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+ more m68k mess... ignore :)
git-svn-id: trunk@2384 -
This commit is contained in:
Károly Balogh
parent
56d3bf1403
commit
37024dc4d0
@ -107,6 +107,61 @@ type
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globtype;
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{$WARNING FIX ME!! useful for debug, remove it, same table as in agcpugas }
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const
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gas_op2str:op2strtable=
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{ warning: CPU32 opcodes are not fully compatible with the MC68020. }
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{ 68000 only opcodes }
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('abcd',
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'add','adda','addi','addq','addx','and','andi',
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'asl','asr','bcc','bcs','beq','bge','bgt','bhi',
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'ble','bls','blt','bmi','bne','bpl','bvc','bvs',
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'bchg','bclr','bra','bset','bsr','btst','chk',
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'clr','cmp','cmpa','cmpi','cmpm','dbcc','dbcs','dbeq','dbge',
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'dbgt','dbhi','dble','dbls','dblt','dbmi','dbne','dbra',
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'dbpl','dbt','dbvc','dbvs','dbf','divs','divu',
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'eor','eori','exg','illegal','ext','jmp','jsr',
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'lea','link','lsl','lsr','move','movea','movei','moveq',
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'movem','movep','muls','mulu','nbcd','neg','negx',
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'nop','not','or','ori','pea','rol','ror','roxl',
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'roxr','rtr','rts','sbcd','scc','scs','seq','sge',
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'sgt','shi','sle','sls','slt','smi','sne',
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'spl','st','svc','svs','sf','sub','suba','subi','subq',
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'subx','swap','tas','trap','trapv','tst','unlk',
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'rte','reset','stop',
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{ mc68010 instructions }
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'bkpt','movec','moves','rtd',
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{ mc68020 instructions }
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'bfchg','bfclr','bfexts','bfextu','bfffo',
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'bfins','bfset','bftst','callm','cas','cas2',
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'chk2','cmp2','divsl','divul','extb','pack','rtm',
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'trapcc','tracs','trapeq','trapf','trapge','trapgt',
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'traphi','traple','trapls','traplt','trapmi','trapne',
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'trappl','trapt','trapvc','trapvs','unpk',
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{ fpu processor instructions - directly supported only. }
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{ ieee aware and misc. condition codes not supported }
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'fabs','fadd',
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'fbeq','fbne','fbngt','fbgt','fbge','fbnge',
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'fblt','fbnlt','fble','fbgl','fbngl','fbgle','fbngle',
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'fdbeq','fdbne','fdbgt','fdbngt','fdbge','fdbnge',
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'fdblt','fdbnlt','fdble','fdbgl','fdbngl','fdbgle','fdbngle',
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'fseq','fsne','fsgt','fsngt','fsge','fsnge',
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'fslt','fsnlt','fsle','fsgl','fsngl','fsgle','fsngle',
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'fcmp','fdiv','fmove','fmovem',
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'fmul','fneg','fnop','fsqrt','fsub','fsgldiv',
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'fsflmul','ftst',
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'ftrapeq','ftrapne','ftrapgt','ftrapngt','ftrapge','ftrapnge',
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'ftraplt','ftrapnlt','ftraple','ftrapgl','ftrapngl','ftrapgle','ftrapngle',
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{ protected instructions }
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'cprestore','cpsave',
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{ fpu unit protected instructions }
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{ and 68030/68851 common mmu instructions }
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{ (this may include 68040 mmu instructions) }
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'frestore','fsave','pflush','pflusha','pload','pmove','ptest',
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{ useful for assembly language output }
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'label','none','db','s','b','fb');
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{*****************************************************************************
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Taicpu Constructors
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*****************************************************************************}
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@ -451,7 +506,8 @@ type
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function taicpu.spilling_get_operation_type(opnr: longint): topertype;
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begin
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case opcode of
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A_MOVE, A_MOVEQ, A_ADD, A_ADDQ, A_SUB, A_SUBQ:
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A_MOVE, A_MOVEQ, A_ADD, A_ADDQ, A_ADDX, A_SUB, A_SUBQ,
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A_AND, A_LSR, A_LSL, A_ASR, A_ASL, A_EOR, A_EORI:
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if opnr=0 then begin
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// writeln('move/etc write');
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result:=operand_write;
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@ -459,8 +515,12 @@ type
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// writeln('move/etc read');
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result:=operand_read;
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end;
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A_TST,A_CMP,A_CMPI:
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result:=operand_read;
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A_CLR,A_NEG:
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result:=operand_write;
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else
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writeln('other opcode: ',dword(opcode),' (faked value returned)',opnr);
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writeln('other opcode: ',gas_op2str[opcode],' (faked value returned)',opnr);
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result:=operand_write;
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end;
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// fake
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@ -474,7 +534,10 @@ type
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case getregtype(r) of
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R_INTREGISTER :
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result:=taicpu.op_ref_reg(A_MOVE,S_L,ref,r);
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R_FPUREGISTER : begin end;
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R_FPUREGISTER : begin
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// is this correct?
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result:=taicpu.op_ref_reg(A_FMOVE,S_L,ref,r);
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end;
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end;
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{
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case getregtype(r) of
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@ -506,7 +569,7 @@ type
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result:=taicpu.op_reg_ref(A_MOVE,S_L,r,ref);
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R_FPUREGISTER :
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begin
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// result:=taicpu.op_reg_ref(A_FMOVE,R_SUBFS,r,ref);
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result:=taicpu.op_reg_ref(A_FMOVE,S_L,r,ref);
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end;
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end;
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{case getregtype(r) of
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@ -420,7 +420,8 @@ implementation
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cgsize2subreg:=R_SUBWHOLE;
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end;
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else begin
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writeln('miafasz?');
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writeln('hmm!?');
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// this supposed to be debug
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// p:=nil; dword(p^):=0;
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// internalerror(200301231);
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cgsize2subreg:=R_SUBWHOLE;
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@ -35,6 +35,7 @@ interface
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function getresflags(unsigned: boolean) : tresflags;
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protected
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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@ -177,6 +178,38 @@ implementation
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end;
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procedure t68kaddnode.second_cmpfloat;
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begin
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pass_left_right;
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{
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if (nf_swaped in flags) then
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swapleftright;
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}
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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location_force_fpureg(exprasmlist,left.location,true);
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location_force_fpureg(exprasmlist,right.location,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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{
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if nodetype in [equaln,unequaln] then
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg(A_CMF,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resulttype.def)]))
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else
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg(A_CMFE,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resulttype.def)]));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(false);
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}
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end;
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{*****************************************************************************
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Smallsets
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@ -405,8 +438,11 @@ implementation
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procedure t68kaddnode.second_cmp64bit;
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begin
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writeln('second_cmp64bit');
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(* load_left_right(true,false);
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pass_left_right;
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// load_left_right(true,false);
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(*
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case nodetype of
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ltn,lten,
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gtn,gten:
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@ -501,6 +537,7 @@ implementation
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location_reset(location,LOC_JUMP,OS_NO);
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*)
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location_reset(location,LOC_JUMP,OS_NO);
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writeln('second_cmp64_exit');
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end;
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