diff --git a/.gitattributes b/.gitattributes index 9dfc8de95f..68e808b4f6 100644 --- a/.gitattributes +++ b/.gitattributes @@ -16104,6 +16104,7 @@ tests/test/units/cocoaall/tw36362.pp svneol=native#text/plain tests/test/units/cpu/tcpu1.pp svneol=native#text/pascal tests/test/units/crt/tcrt.pp svneol=native#text/plain tests/test/units/crt/tctrlc.pp svneol=native#text/plain +tests/test/units/dateutil/test_scandatetime_ampm.pas svneol=native#text/plain tests/test/units/dateutil/testscandatetime.pas svneol=native#text/plain tests/test/units/dateutil/tunitdt1.pp svneol=native#text/pascal tests/test/units/dos/hello.pp svneol=native#text/plain diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas index 8026fe4558..94caeb4744 100644 --- a/compiler/arm/aasmcpu.pas +++ b/compiler/arm/aasmcpu.pas @@ -2204,7 +2204,6 @@ implementation IF_ARMv4, IF_ARMv4, IF_ARMv4T or IF_ARMv4, - IF_ARMv4T or IF_ARMv4 or IF_ARMv5, IF_ARMv4T or IF_ARMv4 or IF_ARMv5 or IF_ARMv5T, IF_ARMv4T or IF_ARMv4 or IF_ARMv5 or IF_ARMv5T or IF_ARMv5TE, IF_ARMv4T or IF_ARMv4 or IF_ARMv5 or IF_ARMv5T or IF_ARMv5TE or IF_ARMv5TEJ, diff --git a/compiler/arm/agarmgas.pas b/compiler/arm/agarmgas.pas index c531f7a899..8f2f89cded 100644 --- a/compiler/arm/agarmgas.pas +++ b/compiler/arm/agarmgas.pas @@ -64,7 +64,6 @@ unit agarmgas; 'armv3', 'armv4', 'armv4t', - 'armv5', 'armv5t', 'armv5te', 'armv5tej', diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas index b6a94a8cb6..31ab0237a4 100644 --- a/compiler/arm/cgcpu.pas +++ b/compiler/arm/cgcpu.pas @@ -294,7 +294,8 @@ unit cgcpu; rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE, [RS_R0,RS_R1,RS_R2,RS_R3,RS_R9,RS_R12,RS_R4,RS_R5,RS_R6,RS_R8, RS_R10,RS_R11,RS_R14],first_int_imreg,[]); - rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE, + if FPUARM_HAS_FPA in fpu_capabilities[current_settings.fputype] then + rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE, [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]); { The register allocator currently cannot deal with multiple non-overlapping subregs per register, so we can only use @@ -306,7 +307,7 @@ unit cgcpu; RS_D16,RS_D17,RS_D18,RS_D19,RS_D20,RS_D21,RS_D22,RS_D23,RS_D24,RS_D25,RS_D26,RS_D27,RS_D28,RS_D29,RS_D30,RS_D31, RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15 ],first_mm_imreg,[]) - else + else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD, [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15],first_mm_imreg,[]); end; @@ -4329,7 +4330,8 @@ unit cgcpu; rg[R_INTREGISTER]:=trgintcputhumb2.create(R_INTREGISTER,R_SUBWHOLE, [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8, RS_R10,RS_R12,RS_R14],first_int_imreg,[]); - rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE, + if FPUARM_HAS_FPA in fpu_capabilities[current_settings.fputype] then + rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE, [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]); if (FPUARM_HAS_32REGS in fpu_capabilities[current_settings.fputype]) and @@ -4349,10 +4351,7 @@ unit cgcpu; rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD, [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7, RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15 - ],first_mm_imreg,[]) - else - rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE, - [RS_S0,RS_S1,RS_R2,RS_R3,RS_R4,RS_S31],first_mm_imreg,[]); + ],first_mm_imreg,[]); end; diff --git a/compiler/arm/cpuinfo.pas b/compiler/arm/cpuinfo.pas index 3dee47ea97..61e97db698 100644 --- a/compiler/arm/cpuinfo.pas +++ b/compiler/arm/cpuinfo.pas @@ -40,7 +40,6 @@ Type cpu_armv3, cpu_armv4, cpu_armv4t, - cpu_armv5, cpu_armv5t, cpu_armv5te, cpu_armv5tej, @@ -556,7 +555,6 @@ Const 'ARMV3', 'ARMV4', 'ARMV4T', - 'ARMV5', 'ARMV5T', 'ARMV5TE', 'ARMV5TEJ', @@ -1058,7 +1056,8 @@ Const type tcpuflags = - (CPUARM_HAS_ALL_MEM, { CPU supports LDRSB/LDRSH/LDRH/STRH instructions } + (CPUARM_HAS_THUMB, { CPU supports THUMB } + CPUARM_HAS_ALL_MEM, { CPU supports LDRSB/LDRSH/LDRH/STRH instructions } CPUARM_HAS_BX, { CPU supports the BX instruction } CPUARM_HAS_BLX, { CPU supports the BLX rX instruction } CPUARM_HAS_BLX_LABEL, { CPU supports the BLX