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* reorganized arm cpu flags

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git-svn-id: trunk@44703 -
This commit is contained in:
florian 2020-04-12 14:24:56 +00:00
parent 497ff94cb0
commit 38c32bcada
5 changed files with 18 additions and 18 deletions
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8
compiler/arm/cpuinfo.pas
View File

@ -1074,9 +1074,9 @@ Const
tfpuflags =
(
FPUARM_HAS_FPA, { fpu is an fpa based FPU }
FPUARM_HAS_VFP_EXTENSION, { fpu is a vfp extension }
FPUARM_HAS_VFP_EXTENSION, { fpu is a vfp extension, it means at least single operation support }
FPUARM_HAS_VFP_DOUBLE, { vfp has double support }
FPUARM_HAS_VFP_SINGLE_ONLY, { vfp has only single support, disjunct to FPUARM_HAS_VFP_DOUBLE, for error checking }
FPUARM_HAS_VFP_DOUBLE_MOVLDST, { vfp has only single support, but MOV, LD, ST can be done on pairs as double }
FPUARM_HAS_32REGS, { vfp has 32 regs, without this flag, 16 are assumed }
FPUARM_HAS_VMOV_CONST, { vmov supports (some) real constants }
FPUARM_HAS_EXCEPTION_TRAPPING, { vfp does exceptions trapping }
@ -1118,9 +1118,9 @@ Const
{ fpu_vfpv3 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST],
{ fpu_neon_vfpv3 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_NEON],
{ fpu_vfpv3_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_VMOV_CONST],
{ fpu_fpv4_s16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_SINGLE_ONLY,FPUARM_HAS_VMOV_CONST],
{ fpu_fpv4_s16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_vfpv4 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_fpv4_sp_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_fpv4_sp_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_neon_vfpv4 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_NEON,FPUARM_HAS_FMA]
);

6
compiler/arm/narmadd.pas
View File

@ -240,7 +240,7 @@ interface
location.register,left.location.register,right.location.register),pf));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
{ force mmreg as location, left right doesn't matter
as both will be in a fpureg }
@ -326,7 +326,7 @@ interface
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VMRS,NR_APSR_nzcv,NR_FPSCR));
location.resflags:=GetFpuResFlags;
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
@ -586,7 +586,7 @@ interface
result := nil;
notnode := false;
if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
if not(FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype]) then
begin
case tfloatdef(left.resultdef).floattype of
s32real:

6
compiler/arm/narmcnv.pas
View File

@ -60,7 +60,7 @@ implementation
{$ifdef cpufpemu}
(current_settings.fputype=fpu_soft) or
{$endif cpufpemu}
(FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype]) then
not(FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype]) then
result:=inherited first_int_to_real
else
begin
@ -109,7 +109,7 @@ implementation
function tarmtypeconvnode.first_real_to_real: tnode;
begin
if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
if not(FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype]) then
begin
case tfloatdef(left.resultdef).floattype of
s32real:
@ -237,7 +237,7 @@ implementation
location.register,left.location.register),
signedprec2vfppf[signed,location.size]));
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
signed:=left.location.size=OS_S32;

12
compiler/arm/narminl.pas
View File

@ -125,7 +125,7 @@ implementation
expectloc:=LOC_FPUREGISTER;
else if FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype] then
expectloc:=LOC_MMREGISTER
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
if tfloatdef(left.resultdef).floattype=s32real then
expectloc:=LOC_MMREGISTER
@ -153,7 +153,7 @@ implementation
expectloc:=LOC_FPUREGISTER;
else if FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype] then
expectloc:=LOC_MMREGISTER
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
if tfloatdef(left.resultdef).floattype=s32real then
expectloc:=LOC_MMREGISTER
@ -181,7 +181,7 @@ implementation
expectloc:=LOC_FPUREGISTER;
else if FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype] then
expectloc:=LOC_MMREGISTER
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
if tfloatdef(left.resultdef).floattype=s32real then
expectloc:=LOC_MMREGISTER
@ -265,7 +265,7 @@ implementation
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register),pf));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register), PF_F32));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
@ -296,7 +296,7 @@ implementation
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register),pf));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register), PF_F32));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
@ -327,7 +327,7 @@ implementation
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register),pf));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[current_settings.fputype] then
begin
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register), PF_F32));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);

4
compiler/arm/narmmat.pas
View File

@ -367,7 +367,7 @@ implementation
exit;
end;
if not(FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[current_settings.fputype]) or
if (FPUARM_HAS_VFP_DOUBLE in fpu_capabilities[current_settings.fputype]) or
(tfloatdef(resultdef).floattype=s32real) then
exit(inherited pass_1);
@ -447,7 +447,7 @@ implementation
location.register,left.location.register), pf));
cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
end
else if FPUARM_HAS_VFP_SINGLE_ONLY in fpu_capabilities[init_settings.fputype] then
else if FPUARM_HAS_VFP_EXTENSION in fpu_capabilities[init_settings.fputype] then
begin
hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
location:=left.location;