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* superregisters also from .dat file

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This commit is contained in:
peter 2003-09-03 16:29:37 +00:00
parent b66e477dd8
commit 3a3bdd95a7
6 changed files with 547 additions and 467 deletions
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8
compiler/cginfo.pas
View File

@ -162,6 +162,9 @@ interface
tsuperregisterset = set of tsuperregister;
const
{ Invalid register number }
RS_INVALID = $ff;
tcgsize2size : Array[tcgsize] of integer =
{ integer values }
(0,1,2,4,8,1,2,4,8,
@ -299,7 +302,10 @@ implementation
end.
{
$Log$
Revision 1.22 2003-09-03 15:55:00 peter
Revision 1.23 2003-09-03 16:29:37 peter
* superregisters also from .dat file
Revision 1.22 2003/09/03 15:55:00 peter
* NEWRA branch merged
Revision 1.21.2.4 2003/09/01 21:02:55 peter

105
compiler/sparc/cpubase.pas
View File

@ -56,85 +56,29 @@ uses
Registers
*****************************************************************************}
type
{ Number of registers used for indexing in tables }
tregisterindex=0..{$i rspnor.inc}-1;
totherregisterset = set of tregisterindex;
const
{ Invalid register number }
RS_INVALID = $ff;
{ Available Superregisters }
{$i rspsup.inc}
{ Integer Super registers }
RS_G0=$00;
RS_G1=$01;
RS_G2=$02;
RS_G3=$03;
RS_G4=$04;
RS_G5=$05;
RS_G6=$06;
RS_G7=$07;
RS_O0=$08;
RS_O1=$09;
RS_O2=$0a;
RS_O3=$0b;
RS_O4=$0c;
RS_O5=$0d;
RS_O6=$0e;
RS_O7=$0f;
RS_L0=$10;
RS_L1=$11;
RS_L2=$12;
RS_L3=$13;
RS_L4=$14;
RS_L5=$15;
RS_L6=$16;
RS_L7=$17;
RS_I0=$18;
RS_I1=$19;
RS_I2=$1a;
RS_I3=$1b;
RS_I4=$1c;
RS_I5=$1d;
RS_I6=$1e;
RS_I7=$1f;
{ No Subregisters }
R_SUBWHOLE=R_SUBNONE;
{ Available Registers }
{$i rspcon.inc}
{ Integer Super registers first and last }
{$warning Supreg shall be $00-$1f}
first_int_supreg = $08;
last_int_supreg = $17;
first_int_supreg = RS_O0;
last_int_supreg = RS_L7;
first_int_imreg = $20;
last_int_imreg = $fe;
{ Float Super registers }
RS_F0=$00;
RS_F1=$01;
RS_F2=$02;
RS_F3=$03;
RS_F4=$04;
RS_F5=$05;
RS_F6=$06;
RS_F7=$07;
RS_F8=$08;
RS_F9=$09;
RS_F10=$0a;
RS_F11=$0b;
RS_F12=$0c;
RS_F13=$0d;
RS_F14=$0e;
RS_F15=$0f;
RS_F16=$10;
RS_F17=$11;
RS_F18=$12;
RS_F19=$13;
RS_F20=$14;
RS_F21=$15;
RS_F22=$16;
RS_F23=$17;
RS_F24=$18;
RS_F25=$19;
RS_F26=$1a;
RS_F27=$1b;
RS_F28=$1c;
RS_F29=$1d;
RS_F30=$1e;
RS_F31=$1f;
{ Float Super register first and last }
first_fpu_supreg = $00;
last_fpu_supreg = $1f;
@ -148,17 +92,6 @@ uses
first_mmx_imreg = RS_INVALID;
last_mmx_imreg = RS_INVALID;
{ No Subregisters }
R_SUBWHOLE=R_SUBNONE;
{ Available Registers }
{$i rspcon.inc}
type
{ Number of registers used for indexing in tables }
tregisterindex=0..{$i rspnor.inc}-1;
const
{$warning TODO Calculate bsstart}
regnumber_count_bsstart = 128;
@ -175,9 +108,6 @@ uses
{$warning FIXME!!}
VOLATILE_FPUREGISTERS = [];
type
totherregisterset = set of tregisterindex;
{*****************************************************************************
Conditions
@ -696,7 +626,10 @@ implementation
end.
{
$Log$
Revision 1.48 2003-09-03 15:55:01 peter
Revision 1.49 2003-09-03 16:29:37 peter
* superregisters also from .dat file
Revision 1.48 2003/09/03 15:55:01 peter
* NEWRA branch merged
Revision 1.47.2.3 2003/09/02 17:49:17 peter

274
compiler/sparc/rspnum.inc
View File

@ -1,138 +1,138 @@
{ don't edit, this file is generated from spreg.dat }
$00000000,
$01000000,
$01000001,
$01000002,
$01000003,
$01000004,
$01000005,
$01000006,
$01000007,
$01000008,
$01000009,
$0100000a,
$0100000b,
$0100000c,
$0100000d,
$0100000e,
$0100000f,
$01000010,
$01000011,
$01000012,
$01000013,
$01000014,
$01000015,
$01000016,
$01000017,
$01000018,
$01000019,
$0100001a,
$0100001b,
$0100001c,
$0100001d,
$0100001e,
$0100001f,
$02000000,
$02000001,
$02000002,
$02000003,
$02000004,
$02000005,
$02000006,
$02000007,
$02000008,
$02000009,
$0200000a,
$0200000b,
$0200000c,
$0200000d,
$0200000e,
$0200000f,
$02000010,
$02000011,
$02000012,
$02000013,
$02000014,
$02000015,
$02000016,
$02000017,
$02000018,
$02000019,
$0200001a,
$0200001b,
$0200001c,
$0200001d,
$0200001e,
$0200001f,
$03000000,
$03000001,
$03000002,
$03000003,
$03000004,
$03000005,
$03000006,
$03000007,
$03000008,
$03000009,
$0300000a,
$0300000b,
$0300000c,
$0300000d,
$0300000e,
$0300000f,
$03000010,
$03000011,
$03000012,
$03000013,
$03000014,
$03000015,
$03000016,
$03000017,
$03000018,
$03000019,
$0300001a,
$0300001b,
$0300001c,
$0300001d,
$0300001e,
$0300001f,
$05000000,
$05000001,
$05000002,
$05000003,
$05000004,
$05000005,
$05000006,
$05000007,
$04000000,
$04000001,
$04000002,
$04000003,
$04000004,
$04000005,
$04000006,
$04000007,
$04000008,
$04000009,
$0400000a,
$0400000b,
$0400000c,
$0400000d,
$0400000e,
$0400000f,
$04000010,
$04000011,
$04000012,
$04000013,
$04000014,
$04000015,
$04000016,
$04000017,
$04000018,
$04000019,
$0400001a,
$0400001b,
$0400001c,
$0400001d,
$0400001e,
$0400001f
NR_NO,
NR_G0,
NR_G1,
NR_G2,
NR_G3,
NR_G4,
NR_G5,
NR_G6,
NR_G7,
NR_O0,
NR_O1,
NR_O2,
NR_O3,
NR_O4,
NR_O5,
NR_O6,
NR_O7,
NR_L0,
NR_L1,
NR_L2,
NR_L3,
NR_L4,
NR_L5,
NR_L6,
NR_L7,
NR_I0,
NR_I1,
NR_I2,
NR_I3,
NR_I4,
NR_I5,
NR_I6,
NR_I7,
NR_F0,
NR_F1,
NR_F2,
NR_F3,
NR_F4,
NR_F5,
NR_F6,
NR_F7,
NR_F8,
NR_F9,
NR_F10,
NR_F11,
NR_F12,
NR_F13,
NR_F14,
NR_F15,
NR_F16,
NR_F17,
NR_F18,
NR_F19,
NR_F20,
NR_F21,
NR_F22,
NR_F23,
NR_F24,
NR_F25,
NR_F26,
NR_F27,
NR_F28,
NR_F29,
NR_F30,
NR_F31,
NR_C0,
NR_C1,
NR_C2,
NR_C3,
NR_C4,
NR_C5,
NR_C6,
NR_C7,
NR_C8,
NR_C9,
NR_C10,
NR_C11,
NR_C12,
NR_C13,
NR_C14,
NR_C15,
NR_C16,
NR_C17,
NR_C18,
NR_C19,
NR_C20,
NR_C21,
NR_C22,
NR_C23,
NR_C24,
NR_C25,
NR_C26,
NR_C27,
NR_C28,
NR_C29,
NR_C30,
NR_C31,
NR_FSR,
NR_FQ,
NR_CSR,
NR_CQ,
NR_PSR,
NR_TBR,
NR_WIM,
NR_Y,
NR_ASR0,
NR_ASR1,
NR_ASR2,
NR_ASR3,
NR_ASR4,
NR_ASR5,
NR_ASR6,
NR_ASR7,
NR_ASR8,
NR_ASR9,
NR_ASR10,
NR_ASR11,
NR_ASR12,
NR_ASR13,
NR_ASR14,
NR_ASR15,
NR_ASR16,
NR_ASR17,
NR_ASR18,
NR_ASR19,
NR_ASR20,
NR_ASR21,
NR_ASR22,
NR_ASR23,
NR_ASR24,
NR_ASR25,
NR_ASR26,
NR_ASR27,
NR_ASR28,
NR_ASR29,
NR_ASR30,
NR_ASR31

208
compiler/sparc/rsprni.inc
View File

@ -1,138 +1,138 @@
{ don't edit, this file is generated from spreg.dat }
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
64,
65,
66,
67,
68,
69,
70,
71,
72,
73,
74,
75,
76,
77,
78,
79,
80,
81,
82,
83,
84,
85,
86,
87,
88,
89,
90,
91,
92,
93,
94,
95,
96,
105,
33,
65,
97,
2,
106,
34,
66,
98,
3,
107,
35,
67,
99,
4,
108,
36,
68,
100,
5,
109,
37,
69,
101,
6,
110,
38,
70,
102,
7,
111,
39,
71,
103,
8,
112,
40,
72,
104,
9,
73,
41,
113,
10,
74,
42,
114,
11,
75,
43,
115,
12,
76,
44,
116,
13,
77,
45,
117,
14,
78,
46,
118,
15,
79,
47,
119,
16,
80,
48,
120,
121,
17,
81,
49,
122,
18,
82,
50,
123,
19,
83,
51,
124,
20,
84,
52,
125,
21,
85,
53,
126,
22,
86,
54,
127,
23,
87,
55,
128,
24,
88,
56,
25,
89,
57,
129,
26,
90,
58,
130,
27,
91,
59,
131,
28,
92,
60,
132,
29,
93,
61,
133,
30,
94,
62,
134,
31,
95,
63,
135,
136,
97,
98,
99,
100,
101,
102,
103,
104
32,
96,
64,
136

138
compiler/sparc/rspsup.inc Normal file
View File

@ -0,0 +1,138 @@
{ don't edit, this file is generated from spreg.dat }
RS_NO = $00;
RS_G0 = $00;
RS_G1 = $01;
RS_G2 = $02;
RS_G3 = $03;
RS_G4 = $04;
RS_G5 = $05;
RS_G6 = $06;
RS_G7 = $07;
RS_O0 = $08;
RS_O1 = $09;
RS_O2 = $0a;
RS_O3 = $0b;
RS_O4 = $0c;
RS_O5 = $0d;
RS_O6 = $0e;
RS_O7 = $0f;
RS_L0 = $10;
RS_L1 = $11;
RS_L2 = $12;
RS_L3 = $13;
RS_L4 = $14;
RS_L5 = $15;
RS_L6 = $16;
RS_L7 = $17;
RS_I0 = $18;
RS_I1 = $19;
RS_I2 = $1a;
RS_I3 = $1b;
RS_I4 = $1c;
RS_I5 = $1d;
RS_I6 = $1e;
RS_I7 = $1f;
RS_F0 = $00;
RS_F1 = $01;
RS_F2 = $02;
RS_F3 = $03;
RS_F4 = $04;
RS_F5 = $05;
RS_F6 = $06;
RS_F7 = $07;
RS_F8 = $08;
RS_F9 = $09;
RS_F10 = $0a;
RS_F11 = $0b;
RS_F12 = $0c;
RS_F13 = $0d;
RS_F14 = $0e;
RS_F15 = $0f;
RS_F16 = $10;
RS_F17 = $11;
RS_F18 = $12;
RS_F19 = $13;
RS_F20 = $14;
RS_F21 = $15;
RS_F22 = $16;
RS_F23 = $17;
RS_F24 = $18;
RS_F25 = $19;
RS_F26 = $1a;
RS_F27 = $1b;
RS_F28 = $1c;
RS_F29 = $1d;
RS_F30 = $1e;
RS_F31 = $1f;
RS_C0 = $00;
RS_C1 = $01;
RS_C2 = $02;
RS_C3 = $03;
RS_C4 = $04;
RS_C5 = $05;
RS_C6 = $06;
RS_C7 = $07;
RS_C8 = $08;
RS_C9 = $09;
RS_C10 = $0a;
RS_C11 = $0b;
RS_C12 = $0c;
RS_C13 = $0d;
RS_C14 = $0e;
RS_C15 = $0f;
RS_C16 = $10;
RS_C17 = $11;
RS_C18 = $12;
RS_C19 = $13;
RS_C20 = $14;
RS_C21 = $15;
RS_C22 = $16;
RS_C23 = $17;
RS_C24 = $18;
RS_C25 = $19;
RS_C26 = $1a;
RS_C27 = $1b;
RS_C28 = $1c;
RS_C29 = $1d;
RS_C30 = $1e;
RS_C31 = $1f;
RS_FSR = $00;
RS_FQ = $01;
RS_CSR = $02;
RS_CQ = $03;
RS_PSR = $04;
RS_TBR = $05;
RS_WIM = $06;
RS_Y = $07;
RS_ASR0 = $00;
RS_ASR1 = $01;
RS_ASR2 = $02;
RS_ASR3 = $03;
RS_ASR4 = $04;
RS_ASR5 = $05;
RS_ASR6 = $06;
RS_ASR7 = $07;
RS_ASR8 = $08;
RS_ASR9 = $09;
RS_ASR10 = $0a;
RS_ASR11 = $0b;
RS_ASR12 = $0c;
RS_ASR13 = $0d;
RS_ASR14 = $0e;
RS_ASR15 = $0f;
RS_ASR16 = $10;
RS_ASR17 = $11;
RS_ASR18 = $12;
RS_ASR19 = $13;
RS_ASR20 = $14;
RS_ASR21 = $15;
RS_ASR22 = $16;
RS_ASR23 = $17;
RS_ASR24 = $18;
RS_ASR25 = $19;
RS_ASR26 = $1a;
RS_ASR27 = $1b;
RS_ASR28 = $1c;
RS_ASR29 = $1d;
RS_ASR30 = $1e;
RS_ASR31 = $1f;

281
compiler/sparc/spreg.dat
View File

@ -4,157 +4,160 @@
; Sparc registers
;
; layout
; <name>,<value>,<stdname>,<stabidx>,<ot value>
; <name>,<regtype>,<regnum>,<stdname>,<stabidx>,<ot value>
;
NR_NO,$00000000,INVALID,-1
NO,$00,$00,INVALID,-1
; Integer registers
NR_G0,$01000000,%g0,1
NR_G1,$01000001,%g1,2
NR_G2,$01000002,%g2,3
NR_G3,$01000003,%g3,4
NR_G4,$01000004,%g4,5
NR_G5,$01000005,%g5,6
NR_G6,$01000006,%g6,7
NR_G7,$01000007,%g7,8
NR_O0,$01000008,%o0,9
NR_O1,$01000009,%o1,10
NR_O2,$0100000a,%o2,11
NR_O3,$0100000b,%o3,12
NR_O4,$0100000c,%o4,13
NR_O5,$0100000d,%o5,14
NR_O6,$0100000e,%o6,15
NR_O7,$0100000f,%o7,16
NR_L0,$01000010,%l0,17
NR_L1,$01000011,%l1,18
NR_L2,$01000012,%l2,19
NR_L3,$01000013,%l3,20
NR_L4,$01000014,%l4,21
NR_L5,$01000015,%l5,22
NR_L6,$01000016,%l6,23
NR_L7,$01000017,%l7,24
NR_I0,$01000018,%i0,25
NR_I1,$01000019,%i1,26
NR_I2,$0100001a,%i2,27
NR_I3,$0100001b,%i3,28
NR_I4,$0100001c,%i4,29
NR_I5,$0100001d,%i5,30
NR_I6,$0100001e,%i6,31
NR_I7,$0100001f,%i7,32
G0,$01,$00,%g0,1
G1,$01,$01,%g1,2
G2,$01,$02,%g2,3
G3,$01,$03,%g3,4
G4,$01,$04,%g4,5
G5,$01,$05,%g5,6
G6,$01,$06,%g6,7
G7,$01,$07,%g7,8
O0,$01,$08,%o0,9
O1,$01,$09,%o1,10
O2,$01,$0a,%o2,11
O3,$01,$0b,%o3,12
O4,$01,$0c,%o4,13
O5,$01,$0d,%o5,14
O6,$01,$0e,%o6,15
O7,$01,$0f,%o7,16
L0,$01,$10,%l0,17
L1,$01,$11,%l1,18
L2,$01,$12,%l2,19
L3,$01,$13,%l3,20
L4,$01,$14,%l4,21
L5,$01,$15,%l5,22
L6,$01,$16,%l6,23
L7,$01,$17,%l7,24
I0,$01,$18,%i0,25
I1,$01,$19,%i1,26
I2,$01,$1a,%i2,27
I3,$01,$1b,%i3,28
I4,$01,$1c,%i4,29
I5,$01,$1d,%i5,30
I6,$01,$1e,%i6,31
I7,$01,$1f,%i7,32
; Float registers
NR_F0,$02000000,%f0,32
NR_F1,$02000001,%f1,32
NR_F2,$02000002,%f2,32
NR_F3,$02000003,%f3,32
NR_F4,$02000004,%f4,32
NR_F5,$02000005,%f5,32
NR_F6,$02000006,%f6,32
NR_F7,$02000007,%f7,32
NR_F8,$02000008,%f8,32
NR_F9,$02000009,%f9,32
NR_F10,$0200000a,%f10,32
NR_F11,$0200000b,%f11,32
NR_F12,$0200000c,%f12,32
NR_F13,$0200000d,%f13,32
NR_F14,$0200000e,%f14,32
NR_F15,$0200000f,%f15,32
NR_F16,$02000010,%f16,32
NR_F17,$02000011,%f17,32
NR_F18,$02000012,%f18,32
NR_F19,$02000013,%f19,32
NR_F20,$02000014,%f20,32
NR_F21,$02000015,%f21,32
NR_F22,$02000016,%f22,32
NR_F23,$02000017,%f23,32
NR_F24,$02000018,%f24,32
NR_F25,$02000019,%f25,32
NR_F26,$0200001a,%f26,32
NR_F27,$0200001b,%f27,32
NR_F28,$0200001c,%f28,32
NR_F29,$0200001d,%f29,32
NR_F30,$0200001e,%f30,32
NR_F31,$0200001f,%f31,32
F0,$02,$00,%f0,32
F1,$02,$01,%f1,32
F2,$02,$02,%f2,32
F3,$02,$03,%f3,32
F4,$02,$04,%f4,32
F5,$02,$05,%f5,32
F6,$02,$06,%f6,32
F7,$02,$07,%f7,32
F8,$02,$08,%f8,32
F9,$02,$09,%f9,32
F10,$02,$0a,%f10,32
F11,$02,$0b,%f11,32
F12,$02,$0c,%f12,32
F13,$02,$0d,%f13,32
F14,$02,$0e,%f14,32
F15,$02,$0f,%f15,32
F16,$02,$10,%f16,32
F17,$02,$11,%f17,32
F18,$02,$12,%f18,32
F19,$02,$13,%f19,32
F20,$02,$14,%f20,32
F21,$02,$15,%f21,32
F22,$02,$16,%f22,32
F23,$02,$17,%f23,32
F24,$02,$18,%f24,32
F25,$02,$19,%f25,32
F26,$02,$1a,%f26,32
F27,$02,$1b,%f27,32
F28,$02,$1c,%f28,32
F29,$02,$1d,%f29,32
F30,$02,$1e,%f30,32
F31,$02,$1f,%f31,32
; Coprocessor registers
NR_C0,$03000000,%c0,32
NR_C1,$03000001,%c1,32
NR_C2,$03000002,%c2,32
NR_C3,$03000003,%c3,32
NR_C4,$03000004,%c4,32
NR_C5,$03000005,%c5,32
NR_C6,$03000006,%c6,32
NR_C7,$03000007,%c7,32
NR_C8,$03000008,%c8,32
NR_C9,$03000009,%c9,32
NR_C10,$0300000a,%c10,32
NR_C11,$0300000b,%c11,32
NR_C12,$0300000c,%c12,32
NR_C13,$0300000d,%c13,32
NR_C14,$0300000e,%c14,32
NR_C15,$0300000f,%c15,32
NR_C16,$03000010,%c16,32
NR_C17,$03000011,%c17,32
NR_C18,$03000012,%c18,32
NR_C19,$03000013,%c19,32
NR_C20,$03000014,%c20,32
NR_C21,$03000015,%c21,32
NR_C22,$03000016,%c22,32
NR_C23,$03000017,%c23,32
NR_C24,$03000018,%c24,32
NR_C25,$03000019,%c25,32
NR_C26,$0300001a,%c26,32
NR_C27,$0300001b,%c27,32
NR_C28,$0300001c,%c28,32
NR_C29,$0300001d,%c29,32
NR_C30,$0300001e,%c30,32
NR_C31,$0300001f,%c31,32
C0,$03,$00,%c0,32
C1,$03,$01,%c1,32
C2,$03,$02,%c2,32
C3,$03,$03,%c3,32
C4,$03,$04,%c4,32
C5,$03,$05,%c5,32
C6,$03,$06,%c6,32
C7,$03,$07,%c7,32
C8,$03,$08,%c8,32
C9,$03,$09,%c9,32
C10,$03,$0a,%c10,32
C11,$03,$0b,%c11,32
C12,$03,$0c,%c12,32
C13,$03,$0d,%c13,32
C14,$03,$0e,%c14,32
C15,$03,$0f,%c15,32
C16,$03,$10,%c16,32
C17,$03,$11,%c17,32
C18,$03,$12,%c18,32
C19,$03,$13,%c19,32
C20,$03,$14,%c20,32
C21,$03,$15,%c21,32
C22,$03,$16,%c22,32
C23,$03,$17,%c23,32
C24,$03,$18,%c24,32
C25,$03,$19,%c25,32
C26,$03,$1a,%c26,32
C27,$03,$1b,%c27,32
C28,$03,$1c,%c28,32
C29,$03,$1d,%c29,32
C30,$03,$1e,%c30,32
C31,$03,$1f,%c31,32
; Special registers
NR_FSR,$05000000,%fsr,64
NR_FQ,$05000001,%fq,65
NR_CSR,$05000002,%csr,64
NR_CQ,$05000003,%cq,65
NR_PSR,$05000004,%psr,64
NR_TBR,$05000005,%tbr,64
NR_WIM,$05000006,%wim,64
NR_Y,$05000007,%y,64
FSR,$05,$00,%fsr,64
FQ,$05,$01,%fq,65
CSR,$05,$02,%csr,64
CQ,$05,$03,%cq,65
PSR,$05,$04,%psr,64
TBR,$05,$05,%tbr,64
WIM,$05,$06,%wim,64
Y,$05,$07,%y,64
; Ancillary State Registers
NR_ASR0,$04000000,%asr0,32
NR_ASR1,$04000001,%asr1,32
NR_ASR2,$04000002,%asr2,32
NR_ASR3,$04000003,%asr3,32
NR_ASR4,$04000004,%asr4,32
NR_ASR5,$04000005,%asr5,32
NR_ASR6,$04000006,%asr6,32
NR_ASR7,$04000007,%asr7,32
NR_ASR8,$04000008,%asr8,32
NR_ASR9,$04000009,%asr9,32
NR_ASR10,$0400000a,%asr10,32
NR_ASR11,$0400000b,%asr11,32
NR_ASR12,$0400000c,%asr12,32
NR_ASR13,$0400000d,%asr13,32
NR_ASR14,$0400000e,%asr14,32
NR_ASR15,$0400000f,%asr15,32
NR_ASR16,$04000010,%asr16,32
NR_ASR17,$04000011,%asr17,32
NR_ASR18,$04000012,%asr18,32
NR_ASR19,$04000013,%asr19,32
NR_ASR20,$04000014,%asr20,32
NR_ASR21,$04000015,%asr21,32
NR_ASR22,$04000016,%asr22,32
NR_ASR23,$04000017,%asr23,32
NR_ASR24,$04000018,%asr24,32
NR_ASR25,$04000019,%asr25,32
NR_ASR26,$0400001a,%asr26,32
NR_ASR27,$0400001b,%asr27,32
NR_ASR28,$0400001c,%asr28,32
NR_ASR29,$0400001d,%asr29,32
NR_ASR30,$0400001e,%asr30,32
NR_ASR31,$0400001f,%asr31,32
ASR0,$04,$00,%asr0,32
ASR1,$04,$01,%asr1,32
ASR2,$04,$02,%asr2,32
ASR3,$04,$03,%asr3,32
ASR4,$04,$04,%asr4,32
ASR5,$04,$05,%asr5,32
ASR6,$04,$06,%asr6,32
ASR7,$04,$07,%asr7,32
ASR8,$04,$08,%asr8,32
ASR9,$04,$09,%asr9,32
ASR10,$04,$0a,%asr10,32
ASR11,$04,$0b,%asr11,32
ASR12,$04,$0c,%asr12,32
ASR13,$04,$0d,%asr13,32
ASR14,$04,$0e,%asr14,32
ASR15,$04,$0f,%asr15,32
ASR16,$04,$10,%asr16,32
ASR17,$04,$11,%asr17,32
ASR18,$04,$12,%asr18,32
ASR19,$04,$13,%asr19,32
ASR20,$04,$14,%asr20,32
ASR21,$04,$15,%asr21,32
ASR22,$04,$16,%asr22,32
ASR23,$04,$17,%asr23,32
ASR24,$04,$18,%asr24,32
ASR25,$04,$19,%asr25,32
ASR26,$04,$1a,%asr26,32
ASR27,$04,$1b,%asr27,32
ASR28,$04,$1c,%asr28,32
ASR29,$04,$1d,%asr29,32
ASR30,$04,$1e,%asr30,32
ASR31,$04,$1f,%asr31,32
;
; $Log$
; Revision 1.2 2003-09-03 15:55:01 peter
; Revision 1.3 2003-09-03 16:29:37 peter
; * superregisters also from .dat file
;
; Revision 1.2 2003/09/03 15:55:01 peter
; * NEWRA branch merged
;
; Revision 1.1.2.2 2003/09/02 17:49:17 peter