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* superregisters also from .dat file
This commit is contained in:
peter
parent
b66e477dd8
commit
3a3bdd95a7
@ -162,6 +162,9 @@ interface
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tsuperregisterset = set of tsuperregister;
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tsuperregisterset = set of tsuperregister;
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const
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const
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{ Invalid register number }
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RS_INVALID = $ff;
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tcgsize2size : Array[tcgsize] of integer =
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tcgsize2size : Array[tcgsize] of integer =
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{ integer values }
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{ integer values }
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(0,1,2,4,8,1,2,4,8,
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(0,1,2,4,8,1,2,4,8,
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@ -299,7 +302,10 @@ implementation
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end.
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end.
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{
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{
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$Log$
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$Log$
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Revision 1.22 2003-09-03 15:55:00 peter
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Revision 1.23 2003-09-03 16:29:37 peter
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* superregisters also from .dat file
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Revision 1.22 2003/09/03 15:55:00 peter
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* NEWRA branch merged
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* NEWRA branch merged
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Revision 1.21.2.4 2003/09/01 21:02:55 peter
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Revision 1.21.2.4 2003/09/01 21:02:55 peter
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@ -56,85 +56,29 @@ uses
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Registers
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Registers
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*****************************************************************************}
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*****************************************************************************}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rspnor.inc}-1;
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totherregisterset = set of tregisterindex;
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const
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const
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{ Invalid register number }
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{ Available Superregisters }
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RS_INVALID = $ff;
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{$i rspsup.inc}
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{ Integer Super registers }
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{ No Subregisters }
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RS_G0=$00;
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R_SUBWHOLE=R_SUBNONE;
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RS_G1=$01;
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RS_G2=$02;
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RS_G3=$03;
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RS_G4=$04;
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RS_G5=$05;
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RS_G6=$06;
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RS_G7=$07;
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RS_O0=$08;
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RS_O1=$09;
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RS_O2=$0a;
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RS_O3=$0b;
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RS_O4=$0c;
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RS_O5=$0d;
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RS_O6=$0e;
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RS_O7=$0f;
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RS_L0=$10;
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RS_L1=$11;
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RS_L2=$12;
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RS_L3=$13;
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RS_L4=$14;
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RS_L5=$15;
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RS_L6=$16;
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RS_L7=$17;
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RS_I0=$18;
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RS_I1=$19;
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RS_I2=$1a;
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RS_I3=$1b;
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RS_I4=$1c;
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RS_I5=$1d;
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RS_I6=$1e;
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RS_I7=$1f;
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{ Available Registers }
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{$i rspcon.inc}
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{ Integer Super registers first and last }
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{$warning Supreg shall be $00-$1f}
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{$warning Supreg shall be $00-$1f}
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first_int_supreg = $08;
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first_int_supreg = RS_O0;
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last_int_supreg = $17;
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last_int_supreg = RS_L7;
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first_int_imreg = $20;
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first_int_imreg = $20;
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last_int_imreg = $fe;
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last_int_imreg = $fe;
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{ Float Super registers }
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RS_F0=$00;
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RS_F1=$01;
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RS_F2=$02;
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RS_F3=$03;
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RS_F4=$04;
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RS_F5=$05;
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RS_F6=$06;
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RS_F7=$07;
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RS_F8=$08;
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RS_F9=$09;
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RS_F10=$0a;
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RS_F11=$0b;
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RS_F12=$0c;
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RS_F13=$0d;
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RS_F14=$0e;
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RS_F15=$0f;
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RS_F16=$10;
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RS_F17=$11;
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RS_F18=$12;
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RS_F19=$13;
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RS_F20=$14;
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RS_F21=$15;
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RS_F22=$16;
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RS_F23=$17;
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RS_F24=$18;
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RS_F25=$19;
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RS_F26=$1a;
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RS_F27=$1b;
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RS_F28=$1c;
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RS_F29=$1d;
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RS_F30=$1e;
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RS_F31=$1f;
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{ Float Super register first and last }
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{ Float Super register first and last }
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first_fpu_supreg = $00;
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first_fpu_supreg = $00;
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last_fpu_supreg = $1f;
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last_fpu_supreg = $1f;
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@ -148,17 +92,6 @@ uses
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first_mmx_imreg = RS_INVALID;
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first_mmx_imreg = RS_INVALID;
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last_mmx_imreg = RS_INVALID;
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last_mmx_imreg = RS_INVALID;
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{ No Subregisters }
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R_SUBWHOLE=R_SUBNONE;
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{ Available Registers }
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{$i rspcon.inc}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rspnor.inc}-1;
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const
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{$warning TODO Calculate bsstart}
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{$warning TODO Calculate bsstart}
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regnumber_count_bsstart = 128;
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regnumber_count_bsstart = 128;
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@ -175,9 +108,6 @@ uses
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{$warning FIXME!!}
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{$warning FIXME!!}
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VOLATILE_FPUREGISTERS = [];
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VOLATILE_FPUREGISTERS = [];
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type
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totherregisterset = set of tregisterindex;
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{*****************************************************************************
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{*****************************************************************************
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Conditions
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Conditions
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@ -696,7 +626,10 @@ implementation
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end.
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end.
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{
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{
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$Log$
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$Log$
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Revision 1.48 2003-09-03 15:55:01 peter
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Revision 1.49 2003-09-03 16:29:37 peter
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* superregisters also from .dat file
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Revision 1.48 2003/09/03 15:55:01 peter
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* NEWRA branch merged
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* NEWRA branch merged
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Revision 1.47.2.3 2003/09/02 17:49:17 peter
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Revision 1.47.2.3 2003/09/02 17:49:17 peter
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@ -1,138 +1,138 @@
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{ don't edit, this file is generated from spreg.dat }
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{ don't edit, this file is generated from spreg.dat }
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$00000000,
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NR_NO,
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$01000000,
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NR_G0,
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$01000001,
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NR_G1,
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$01000002,
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NR_G2,
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$01000003,
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NR_G3,
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$01000004,
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NR_G4,
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$01000005,
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NR_G5,
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$01000006,
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NR_G6,
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$01000007,
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NR_G7,
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$01000008,
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NR_O0,
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$01000009,
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NR_O1,
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$0100000a,
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NR_O2,
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$0100000b,
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NR_O3,
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$0100000c,
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NR_O4,
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$0100000d,
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NR_O5,
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$0100000e,
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NR_O6,
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$0100000f,
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NR_O7,
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$01000010,
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NR_L0,
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$01000011,
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NR_L1,
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$01000012,
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NR_L2,
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$01000013,
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NR_L3,
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$01000014,
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NR_L4,
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$01000015,
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NR_L5,
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$01000016,
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NR_L6,
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$01000017,
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NR_L7,
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$01000018,
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NR_I0,
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$01000019,
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NR_I1,
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$0100001a,
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NR_I2,
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$0100001b,
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NR_I3,
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$0100001c,
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NR_I4,
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$0100001d,
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NR_I5,
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$0100001e,
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NR_I6,
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$0100001f,
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NR_I7,
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$02000000,
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NR_F0,
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$02000001,
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NR_F1,
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$02000002,
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NR_F2,
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$02000003,
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NR_F3,
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$02000004,
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NR_F4,
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$02000005,
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NR_F5,
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$02000006,
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NR_F6,
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$02000007,
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NR_F7,
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$02000008,
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NR_F8,
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$02000009,
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NR_F9,
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$0200000a,
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NR_F10,
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$0200000b,
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NR_F11,
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$0200000c,
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NR_F12,
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$0200000d,
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NR_F13,
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$0200000e,
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NR_F14,
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$0200000f,
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NR_F15,
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$02000010,
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NR_F16,
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$02000011,
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NR_F17,
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$02000012,
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NR_F18,
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$02000013,
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NR_F19,
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$02000014,
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NR_F20,
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$02000015,
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NR_F21,
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$02000016,
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NR_F22,
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$02000017,
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NR_F23,
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$02000018,
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NR_F24,
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$02000019,
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NR_F25,
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$0200001a,
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NR_F26,
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$0200001b,
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NR_F27,
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$0200001c,
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NR_F28,
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$0200001d,
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NR_F29,
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$0200001e,
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NR_F30,
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$0200001f,
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NR_F31,
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$03000000,
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NR_C0,
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$03000001,
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NR_C1,
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$03000002,
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NR_C2,
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$03000003,
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NR_C3,
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$03000004,
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NR_C4,
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$03000005,
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NR_C5,
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$03000006,
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NR_C6,
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$03000007,
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NR_C7,
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$03000008,
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NR_C8,
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$03000009,
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NR_C9,
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$0300000a,
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NR_C10,
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$0300000b,
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NR_C11,
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$0300000c,
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NR_C12,
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$0300000d,
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NR_C13,
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$0300000e,
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NR_C14,
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$0300000f,
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NR_C15,
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$03000010,
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NR_C16,
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$03000011,
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NR_C17,
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$03000012,
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NR_C18,
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$03000013,
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NR_C19,
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$03000014,
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NR_C20,
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$03000015,
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NR_C21,
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$03000016,
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NR_C22,
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$03000017,
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NR_C23,
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$03000018,
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NR_C24,
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$03000019,
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NR_C25,
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$0300001a,
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NR_C26,
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$0300001b,
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NR_C27,
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$0300001c,
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NR_C28,
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$0300001d,
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NR_C29,
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$0300001e,
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NR_C30,
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$0300001f,
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NR_C31,
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$05000000,
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NR_FSR,
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$05000001,
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NR_FQ,
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$05000002,
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NR_CSR,
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$05000003,
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NR_CQ,
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$05000004,
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NR_PSR,
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$05000005,
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NR_TBR,
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$05000006,
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NR_WIM,
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$05000007,
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NR_Y,
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$04000000,
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NR_ASR0,
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$04000001,
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NR_ASR1,
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$04000002,
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NR_ASR2,
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$04000003,
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NR_ASR3,
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$04000004,
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NR_ASR4,
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$04000005,
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NR_ASR5,
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$04000006,
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NR_ASR6,
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$04000007,
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NR_ASR7,
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$04000008,
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NR_ASR8,
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$04000009,
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NR_ASR9,
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$0400000a,
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NR_ASR10,
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$0400000b,
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NR_ASR11,
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$0400000c,
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NR_ASR12,
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$0400000d,
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NR_ASR13,
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$0400000e,
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NR_ASR14,
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$0400000f,
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NR_ASR15,
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$04000010,
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NR_ASR16,
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$04000011,
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NR_ASR17,
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$04000012,
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NR_ASR18,
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$04000013,
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NR_ASR19,
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$04000014,
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NR_ASR20,
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$04000015,
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NR_ASR21,
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$04000016,
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NR_ASR22,
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$04000017,
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NR_ASR23,
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$04000018,
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NR_ASR24,
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$04000019,
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NR_ASR25,
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$0400001a,
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NR_ASR26,
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$0400001b,
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NR_ASR27,
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$0400001c,
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NR_ASR28,
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$0400001d,
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NR_ASR29,
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$0400001e,
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NR_ASR30,
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$0400001f
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NR_ASR31
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@ -1,138 +1,138 @@
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{ don't edit, this file is generated from spreg.dat }
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{ don't edit, this file is generated from spreg.dat }
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0,
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0,
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1,
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1,
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2,
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3,
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4,
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5,
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6,
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8,
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9,
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10,
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11,
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12,
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13,
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14,
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15,
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16,
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21,
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22,
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26,
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27,
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28,
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29,
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30,
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31,
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32,
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33,
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34,
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36,
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37,
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38,
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39,
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40,
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41,
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42,
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43,
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44,
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45,
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46,
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47,
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48,
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49,
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50,
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51,
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52,
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53,
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54,
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55,
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56,
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57,
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58,
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59,
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60,
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61,
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62,
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63,
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64,
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65,
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66,
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67,
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68,
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69,
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70,
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71,
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|
||||||
72,
|
|
||||||
73,
|
|
||||||
74,
|
|
||||||
75,
|
|
||||||
76,
|
|
||||||
77,
|
|
||||||
78,
|
|
||||||
79,
|
|
||||||
80,
|
|
||||||
81,
|
|
||||||
82,
|
|
||||||
83,
|
|
||||||
84,
|
|
||||||
85,
|
|
||||||
86,
|
|
||||||
87,
|
|
||||||
88,
|
|
||||||
89,
|
|
||||||
90,
|
|
||||||
91,
|
|
||||||
92,
|
|
||||||
93,
|
|
||||||
94,
|
|
||||||
95,
|
|
||||||
96,
|
|
||||||
105,
|
105,
|
||||||
|
33,
|
||||||
|
65,
|
||||||
|
97,
|
||||||
|
2,
|
||||||
106,
|
106,
|
||||||
|
34,
|
||||||
|
66,
|
||||||
|
98,
|
||||||
|
3,
|
||||||
107,
|
107,
|
||||||
|
35,
|
||||||
|
67,
|
||||||
|
99,
|
||||||
|
4,
|
||||||
108,
|
108,
|
||||||
|
36,
|
||||||
|
68,
|
||||||
|
100,
|
||||||
|
5,
|
||||||
109,
|
109,
|
||||||
|
37,
|
||||||
|
69,
|
||||||
|
101,
|
||||||
|
6,
|
||||||
110,
|
110,
|
||||||
|
38,
|
||||||
|
70,
|
||||||
|
102,
|
||||||
|
7,
|
||||||
111,
|
111,
|
||||||
|
39,
|
||||||
|
71,
|
||||||
|
103,
|
||||||
|
8,
|
||||||
112,
|
112,
|
||||||
|
40,
|
||||||
|
72,
|
||||||
|
104,
|
||||||
|
9,
|
||||||
|
73,
|
||||||
|
41,
|
||||||
113,
|
113,
|
||||||
|
10,
|
||||||
|
74,
|
||||||
|
42,
|
||||||
114,
|
114,
|
||||||
|
11,
|
||||||
|
75,
|
||||||
|
43,
|
||||||
115,
|
115,
|
||||||
|
12,
|
||||||
|
76,
|
||||||
|
44,
|
||||||
116,
|
116,
|
||||||
|
13,
|
||||||
|
77,
|
||||||
|
45,
|
||||||
117,
|
117,
|
||||||
|
14,
|
||||||
|
78,
|
||||||
|
46,
|
||||||
118,
|
118,
|
||||||
|
15,
|
||||||
|
79,
|
||||||
|
47,
|
||||||
119,
|
119,
|
||||||
|
16,
|
||||||
|
80,
|
||||||
|
48,
|
||||||
120,
|
120,
|
||||||
121,
|
121,
|
||||||
|
17,
|
||||||
|
81,
|
||||||
|
49,
|
||||||
122,
|
122,
|
||||||
|
18,
|
||||||
|
82,
|
||||||
|
50,
|
||||||
123,
|
123,
|
||||||
|
19,
|
||||||
|
83,
|
||||||
|
51,
|
||||||
124,
|
124,
|
||||||
|
20,
|
||||||
|
84,
|
||||||
|
52,
|
||||||
125,
|
125,
|
||||||
|
21,
|
||||||
|
85,
|
||||||
|
53,
|
||||||
126,
|
126,
|
||||||
|
22,
|
||||||
|
86,
|
||||||
|
54,
|
||||||
127,
|
127,
|
||||||
|
23,
|
||||||
|
87,
|
||||||
|
55,
|
||||||
128,
|
128,
|
||||||
|
24,
|
||||||
|
88,
|
||||||
|
56,
|
||||||
|
25,
|
||||||
|
89,
|
||||||
|
57,
|
||||||
129,
|
129,
|
||||||
|
26,
|
||||||
|
90,
|
||||||
|
58,
|
||||||
130,
|
130,
|
||||||
|
27,
|
||||||
|
91,
|
||||||
|
59,
|
||||||
131,
|
131,
|
||||||
|
28,
|
||||||
|
92,
|
||||||
|
60,
|
||||||
132,
|
132,
|
||||||
|
29,
|
||||||
|
93,
|
||||||
|
61,
|
||||||
133,
|
133,
|
||||||
|
30,
|
||||||
|
94,
|
||||||
|
62,
|
||||||
134,
|
134,
|
||||||
|
31,
|
||||||
|
95,
|
||||||
|
63,
|
||||||
135,
|
135,
|
||||||
136,
|
32,
|
||||||
97,
|
96,
|
||||||
98,
|
64,
|
||||||
99,
|
136
|
||||||
100,
|
|
||||||
101,
|
|
||||||
102,
|
|
||||||
103,
|
|
||||||
104
|
|
||||||
|
|||||||
138
compiler/sparc/rspsup.inc
Normal file
138
compiler/sparc/rspsup.inc
Normal file
@ -0,0 +1,138 @@
|
|||||||
|
{ don't edit, this file is generated from spreg.dat }
|
||||||
|
RS_NO = $00;
|
||||||
|
RS_G0 = $00;
|
||||||
|
RS_G1 = $01;
|
||||||
|
RS_G2 = $02;
|
||||||
|
RS_G3 = $03;
|
||||||
|
RS_G4 = $04;
|
||||||
|
RS_G5 = $05;
|
||||||
|
RS_G6 = $06;
|
||||||
|
RS_G7 = $07;
|
||||||
|
RS_O0 = $08;
|
||||||
|
RS_O1 = $09;
|
||||||
|
RS_O2 = $0a;
|
||||||
|
RS_O3 = $0b;
|
||||||
|
RS_O4 = $0c;
|
||||||
|
RS_O5 = $0d;
|
||||||
|
RS_O6 = $0e;
|
||||||
|
RS_O7 = $0f;
|
||||||
|
RS_L0 = $10;
|
||||||
|
RS_L1 = $11;
|
||||||
|
RS_L2 = $12;
|
||||||
|
RS_L3 = $13;
|
||||||
|
RS_L4 = $14;
|
||||||
|
RS_L5 = $15;
|
||||||
|
RS_L6 = $16;
|
||||||
|
RS_L7 = $17;
|
||||||
|
RS_I0 = $18;
|
||||||
|
RS_I1 = $19;
|
||||||
|
RS_I2 = $1a;
|
||||||
|
RS_I3 = $1b;
|
||||||
|
RS_I4 = $1c;
|
||||||
|
RS_I5 = $1d;
|
||||||
|
RS_I6 = $1e;
|
||||||
|
RS_I7 = $1f;
|
||||||
|
RS_F0 = $00;
|
||||||
|
RS_F1 = $01;
|
||||||
|
RS_F2 = $02;
|
||||||
|
RS_F3 = $03;
|
||||||
|
RS_F4 = $04;
|
||||||
|
RS_F5 = $05;
|
||||||
|
RS_F6 = $06;
|
||||||
|
RS_F7 = $07;
|
||||||
|
RS_F8 = $08;
|
||||||
|
RS_F9 = $09;
|
||||||
|
RS_F10 = $0a;
|
||||||
|
RS_F11 = $0b;
|
||||||
|
RS_F12 = $0c;
|
||||||
|
RS_F13 = $0d;
|
||||||
|
RS_F14 = $0e;
|
||||||
|
RS_F15 = $0f;
|
||||||
|
RS_F16 = $10;
|
||||||
|
RS_F17 = $11;
|
||||||
|
RS_F18 = $12;
|
||||||
|
RS_F19 = $13;
|
||||||
|
RS_F20 = $14;
|
||||||
|
RS_F21 = $15;
|
||||||
|
RS_F22 = $16;
|
||||||
|
RS_F23 = $17;
|
||||||
|
RS_F24 = $18;
|
||||||
|
RS_F25 = $19;
|
||||||
|
RS_F26 = $1a;
|
||||||
|
RS_F27 = $1b;
|
||||||
|
RS_F28 = $1c;
|
||||||
|
RS_F29 = $1d;
|
||||||
|
RS_F30 = $1e;
|
||||||
|
RS_F31 = $1f;
|
||||||
|
RS_C0 = $00;
|
||||||
|
RS_C1 = $01;
|
||||||
|
RS_C2 = $02;
|
||||||
|
RS_C3 = $03;
|
||||||
|
RS_C4 = $04;
|
||||||
|
RS_C5 = $05;
|
||||||
|
RS_C6 = $06;
|
||||||
|
RS_C7 = $07;
|
||||||
|
RS_C8 = $08;
|
||||||
|
RS_C9 = $09;
|
||||||
|
RS_C10 = $0a;
|
||||||
|
RS_C11 = $0b;
|
||||||
|
RS_C12 = $0c;
|
||||||
|
RS_C13 = $0d;
|
||||||
|
RS_C14 = $0e;
|
||||||
|
RS_C15 = $0f;
|
||||||
|
RS_C16 = $10;
|
||||||
|
RS_C17 = $11;
|
||||||
|
RS_C18 = $12;
|
||||||
|
RS_C19 = $13;
|
||||||
|
RS_C20 = $14;
|
||||||
|
RS_C21 = $15;
|
||||||
|
RS_C22 = $16;
|
||||||
|
RS_C23 = $17;
|
||||||
|
RS_C24 = $18;
|
||||||
|
RS_C25 = $19;
|
||||||
|
RS_C26 = $1a;
|
||||||
|
RS_C27 = $1b;
|
||||||
|
RS_C28 = $1c;
|
||||||
|
RS_C29 = $1d;
|
||||||
|
RS_C30 = $1e;
|
||||||
|
RS_C31 = $1f;
|
||||||
|
RS_FSR = $00;
|
||||||
|
RS_FQ = $01;
|
||||||
|
RS_CSR = $02;
|
||||||
|
RS_CQ = $03;
|
||||||
|
RS_PSR = $04;
|
||||||
|
RS_TBR = $05;
|
||||||
|
RS_WIM = $06;
|
||||||
|
RS_Y = $07;
|
||||||
|
RS_ASR0 = $00;
|
||||||
|
RS_ASR1 = $01;
|
||||||
|
RS_ASR2 = $02;
|
||||||
|
RS_ASR3 = $03;
|
||||||
|
RS_ASR4 = $04;
|
||||||
|
RS_ASR5 = $05;
|
||||||
|
RS_ASR6 = $06;
|
||||||
|
RS_ASR7 = $07;
|
||||||
|
RS_ASR8 = $08;
|
||||||
|
RS_ASR9 = $09;
|
||||||
|
RS_ASR10 = $0a;
|
||||||
|
RS_ASR11 = $0b;
|
||||||
|
RS_ASR12 = $0c;
|
||||||
|
RS_ASR13 = $0d;
|
||||||
|
RS_ASR14 = $0e;
|
||||||
|
RS_ASR15 = $0f;
|
||||||
|
RS_ASR16 = $10;
|
||||||
|
RS_ASR17 = $11;
|
||||||
|
RS_ASR18 = $12;
|
||||||
|
RS_ASR19 = $13;
|
||||||
|
RS_ASR20 = $14;
|
||||||
|
RS_ASR21 = $15;
|
||||||
|
RS_ASR22 = $16;
|
||||||
|
RS_ASR23 = $17;
|
||||||
|
RS_ASR24 = $18;
|
||||||
|
RS_ASR25 = $19;
|
||||||
|
RS_ASR26 = $1a;
|
||||||
|
RS_ASR27 = $1b;
|
||||||
|
RS_ASR28 = $1c;
|
||||||
|
RS_ASR29 = $1d;
|
||||||
|
RS_ASR30 = $1e;
|
||||||
|
RS_ASR31 = $1f;
|
||||||
@ -4,157 +4,160 @@
|
|||||||
; Sparc registers
|
; Sparc registers
|
||||||
;
|
;
|
||||||
; layout
|
; layout
|
||||||
; <name>,<value>,<stdname>,<stabidx>,<ot value>
|
; <name>,<regtype>,<regnum>,<stdname>,<stabidx>,<ot value>
|
||||||
;
|
;
|
||||||
NR_NO,$00000000,INVALID,-1
|
NO,$00,$00,INVALID,-1
|
||||||
; Integer registers
|
; Integer registers
|
||||||
NR_G0,$01000000,%g0,1
|
G0,$01,$00,%g0,1
|
||||||
NR_G1,$01000001,%g1,2
|
G1,$01,$01,%g1,2
|
||||||
NR_G2,$01000002,%g2,3
|
G2,$01,$02,%g2,3
|
||||||
NR_G3,$01000003,%g3,4
|
G3,$01,$03,%g3,4
|
||||||
NR_G4,$01000004,%g4,5
|
G4,$01,$04,%g4,5
|
||||||
NR_G5,$01000005,%g5,6
|
G5,$01,$05,%g5,6
|
||||||
NR_G6,$01000006,%g6,7
|
G6,$01,$06,%g6,7
|
||||||
NR_G7,$01000007,%g7,8
|
G7,$01,$07,%g7,8
|
||||||
NR_O0,$01000008,%o0,9
|
O0,$01,$08,%o0,9
|
||||||
NR_O1,$01000009,%o1,10
|
O1,$01,$09,%o1,10
|
||||||
NR_O2,$0100000a,%o2,11
|
O2,$01,$0a,%o2,11
|
||||||
NR_O3,$0100000b,%o3,12
|
O3,$01,$0b,%o3,12
|
||||||
NR_O4,$0100000c,%o4,13
|
O4,$01,$0c,%o4,13
|
||||||
NR_O5,$0100000d,%o5,14
|
O5,$01,$0d,%o5,14
|
||||||
NR_O6,$0100000e,%o6,15
|
O6,$01,$0e,%o6,15
|
||||||
NR_O7,$0100000f,%o7,16
|
O7,$01,$0f,%o7,16
|
||||||
NR_L0,$01000010,%l0,17
|
L0,$01,$10,%l0,17
|
||||||
NR_L1,$01000011,%l1,18
|
L1,$01,$11,%l1,18
|
||||||
NR_L2,$01000012,%l2,19
|
L2,$01,$12,%l2,19
|
||||||
NR_L3,$01000013,%l3,20
|
L3,$01,$13,%l3,20
|
||||||
NR_L4,$01000014,%l4,21
|
L4,$01,$14,%l4,21
|
||||||
NR_L5,$01000015,%l5,22
|
L5,$01,$15,%l5,22
|
||||||
NR_L6,$01000016,%l6,23
|
L6,$01,$16,%l6,23
|
||||||
NR_L7,$01000017,%l7,24
|
L7,$01,$17,%l7,24
|
||||||
NR_I0,$01000018,%i0,25
|
I0,$01,$18,%i0,25
|
||||||
NR_I1,$01000019,%i1,26
|
I1,$01,$19,%i1,26
|
||||||
NR_I2,$0100001a,%i2,27
|
I2,$01,$1a,%i2,27
|
||||||
NR_I3,$0100001b,%i3,28
|
I3,$01,$1b,%i3,28
|
||||||
NR_I4,$0100001c,%i4,29
|
I4,$01,$1c,%i4,29
|
||||||
NR_I5,$0100001d,%i5,30
|
I5,$01,$1d,%i5,30
|
||||||
NR_I6,$0100001e,%i6,31
|
I6,$01,$1e,%i6,31
|
||||||
NR_I7,$0100001f,%i7,32
|
I7,$01,$1f,%i7,32
|
||||||
; Float registers
|
; Float registers
|
||||||
NR_F0,$02000000,%f0,32
|
F0,$02,$00,%f0,32
|
||||||
NR_F1,$02000001,%f1,32
|
F1,$02,$01,%f1,32
|
||||||
NR_F2,$02000002,%f2,32
|
F2,$02,$02,%f2,32
|
||||||
NR_F3,$02000003,%f3,32
|
F3,$02,$03,%f3,32
|
||||||
NR_F4,$02000004,%f4,32
|
F4,$02,$04,%f4,32
|
||||||
NR_F5,$02000005,%f5,32
|
F5,$02,$05,%f5,32
|
||||||
NR_F6,$02000006,%f6,32
|
F6,$02,$06,%f6,32
|
||||||
NR_F7,$02000007,%f7,32
|
F7,$02,$07,%f7,32
|
||||||
NR_F8,$02000008,%f8,32
|
F8,$02,$08,%f8,32
|
||||||
NR_F9,$02000009,%f9,32
|
F9,$02,$09,%f9,32
|
||||||
NR_F10,$0200000a,%f10,32
|
F10,$02,$0a,%f10,32
|
||||||
NR_F11,$0200000b,%f11,32
|
F11,$02,$0b,%f11,32
|
||||||
NR_F12,$0200000c,%f12,32
|
F12,$02,$0c,%f12,32
|
||||||
NR_F13,$0200000d,%f13,32
|
F13,$02,$0d,%f13,32
|
||||||
NR_F14,$0200000e,%f14,32
|
F14,$02,$0e,%f14,32
|
||||||
NR_F15,$0200000f,%f15,32
|
F15,$02,$0f,%f15,32
|
||||||
NR_F16,$02000010,%f16,32
|
F16,$02,$10,%f16,32
|
||||||
NR_F17,$02000011,%f17,32
|
F17,$02,$11,%f17,32
|
||||||
NR_F18,$02000012,%f18,32
|
F18,$02,$12,%f18,32
|
||||||
NR_F19,$02000013,%f19,32
|
F19,$02,$13,%f19,32
|
||||||
NR_F20,$02000014,%f20,32
|
F20,$02,$14,%f20,32
|
||||||
NR_F21,$02000015,%f21,32
|
F21,$02,$15,%f21,32
|
||||||
NR_F22,$02000016,%f22,32
|
F22,$02,$16,%f22,32
|
||||||
NR_F23,$02000017,%f23,32
|
F23,$02,$17,%f23,32
|
||||||
NR_F24,$02000018,%f24,32
|
F24,$02,$18,%f24,32
|
||||||
NR_F25,$02000019,%f25,32
|
F25,$02,$19,%f25,32
|
||||||
NR_F26,$0200001a,%f26,32
|
F26,$02,$1a,%f26,32
|
||||||
NR_F27,$0200001b,%f27,32
|
F27,$02,$1b,%f27,32
|
||||||
NR_F28,$0200001c,%f28,32
|
F28,$02,$1c,%f28,32
|
||||||
NR_F29,$0200001d,%f29,32
|
F29,$02,$1d,%f29,32
|
||||||
NR_F30,$0200001e,%f30,32
|
F30,$02,$1e,%f30,32
|
||||||
NR_F31,$0200001f,%f31,32
|
F31,$02,$1f,%f31,32
|
||||||
|
|
||||||
; Coprocessor registers
|
; Coprocessor registers
|
||||||
NR_C0,$03000000,%c0,32
|
C0,$03,$00,%c0,32
|
||||||
NR_C1,$03000001,%c1,32
|
C1,$03,$01,%c1,32
|
||||||
NR_C2,$03000002,%c2,32
|
C2,$03,$02,%c2,32
|
||||||
NR_C3,$03000003,%c3,32
|
C3,$03,$03,%c3,32
|
||||||
NR_C4,$03000004,%c4,32
|
C4,$03,$04,%c4,32
|
||||||
NR_C5,$03000005,%c5,32
|
C5,$03,$05,%c5,32
|
||||||
NR_C6,$03000006,%c6,32
|
C6,$03,$06,%c6,32
|
||||||
NR_C7,$03000007,%c7,32
|
C7,$03,$07,%c7,32
|
||||||
NR_C8,$03000008,%c8,32
|
C8,$03,$08,%c8,32
|
||||||
NR_C9,$03000009,%c9,32
|
C9,$03,$09,%c9,32
|
||||||
NR_C10,$0300000a,%c10,32
|
C10,$03,$0a,%c10,32
|
||||||
NR_C11,$0300000b,%c11,32
|
C11,$03,$0b,%c11,32
|
||||||
NR_C12,$0300000c,%c12,32
|
C12,$03,$0c,%c12,32
|
||||||
NR_C13,$0300000d,%c13,32
|
C13,$03,$0d,%c13,32
|
||||||
NR_C14,$0300000e,%c14,32
|
C14,$03,$0e,%c14,32
|
||||||
NR_C15,$0300000f,%c15,32
|
C15,$03,$0f,%c15,32
|
||||||
NR_C16,$03000010,%c16,32
|
C16,$03,$10,%c16,32
|
||||||
NR_C17,$03000011,%c17,32
|
C17,$03,$11,%c17,32
|
||||||
NR_C18,$03000012,%c18,32
|
C18,$03,$12,%c18,32
|
||||||
NR_C19,$03000013,%c19,32
|
C19,$03,$13,%c19,32
|
||||||
NR_C20,$03000014,%c20,32
|
C20,$03,$14,%c20,32
|
||||||
NR_C21,$03000015,%c21,32
|
C21,$03,$15,%c21,32
|
||||||
NR_C22,$03000016,%c22,32
|
C22,$03,$16,%c22,32
|
||||||
NR_C23,$03000017,%c23,32
|
C23,$03,$17,%c23,32
|
||||||
NR_C24,$03000018,%c24,32
|
C24,$03,$18,%c24,32
|
||||||
NR_C25,$03000019,%c25,32
|
C25,$03,$19,%c25,32
|
||||||
NR_C26,$0300001a,%c26,32
|
C26,$03,$1a,%c26,32
|
||||||
NR_C27,$0300001b,%c27,32
|
C27,$03,$1b,%c27,32
|
||||||
NR_C28,$0300001c,%c28,32
|
C28,$03,$1c,%c28,32
|
||||||
NR_C29,$0300001d,%c29,32
|
C29,$03,$1d,%c29,32
|
||||||
NR_C30,$0300001e,%c30,32
|
C30,$03,$1e,%c30,32
|
||||||
NR_C31,$0300001f,%c31,32
|
C31,$03,$1f,%c31,32
|
||||||
|
|
||||||
; Special registers
|
; Special registers
|
||||||
NR_FSR,$05000000,%fsr,64
|
FSR,$05,$00,%fsr,64
|
||||||
NR_FQ,$05000001,%fq,65
|
FQ,$05,$01,%fq,65
|
||||||
NR_CSR,$05000002,%csr,64
|
CSR,$05,$02,%csr,64
|
||||||
NR_CQ,$05000003,%cq,65
|
CQ,$05,$03,%cq,65
|
||||||
NR_PSR,$05000004,%psr,64
|
PSR,$05,$04,%psr,64
|
||||||
NR_TBR,$05000005,%tbr,64
|
TBR,$05,$05,%tbr,64
|
||||||
NR_WIM,$05000006,%wim,64
|
WIM,$05,$06,%wim,64
|
||||||
NR_Y,$05000007,%y,64
|
Y,$05,$07,%y,64
|
||||||
|
|
||||||
; Ancillary State Registers
|
; Ancillary State Registers
|
||||||
NR_ASR0,$04000000,%asr0,32
|
ASR0,$04,$00,%asr0,32
|
||||||
NR_ASR1,$04000001,%asr1,32
|
ASR1,$04,$01,%asr1,32
|
||||||
NR_ASR2,$04000002,%asr2,32
|
ASR2,$04,$02,%asr2,32
|
||||||
NR_ASR3,$04000003,%asr3,32
|
ASR3,$04,$03,%asr3,32
|
||||||
NR_ASR4,$04000004,%asr4,32
|
ASR4,$04,$04,%asr4,32
|
||||||
NR_ASR5,$04000005,%asr5,32
|
ASR5,$04,$05,%asr5,32
|
||||||
NR_ASR6,$04000006,%asr6,32
|
ASR6,$04,$06,%asr6,32
|
||||||
NR_ASR7,$04000007,%asr7,32
|
ASR7,$04,$07,%asr7,32
|
||||||
NR_ASR8,$04000008,%asr8,32
|
ASR8,$04,$08,%asr8,32
|
||||||
NR_ASR9,$04000009,%asr9,32
|
ASR9,$04,$09,%asr9,32
|
||||||
NR_ASR10,$0400000a,%asr10,32
|
ASR10,$04,$0a,%asr10,32
|
||||||
NR_ASR11,$0400000b,%asr11,32
|
ASR11,$04,$0b,%asr11,32
|
||||||
NR_ASR12,$0400000c,%asr12,32
|
ASR12,$04,$0c,%asr12,32
|
||||||
NR_ASR13,$0400000d,%asr13,32
|
ASR13,$04,$0d,%asr13,32
|
||||||
NR_ASR14,$0400000e,%asr14,32
|
ASR14,$04,$0e,%asr14,32
|
||||||
NR_ASR15,$0400000f,%asr15,32
|
ASR15,$04,$0f,%asr15,32
|
||||||
NR_ASR16,$04000010,%asr16,32
|
ASR16,$04,$10,%asr16,32
|
||||||
NR_ASR17,$04000011,%asr17,32
|
ASR17,$04,$11,%asr17,32
|
||||||
NR_ASR18,$04000012,%asr18,32
|
ASR18,$04,$12,%asr18,32
|
||||||
NR_ASR19,$04000013,%asr19,32
|
ASR19,$04,$13,%asr19,32
|
||||||
NR_ASR20,$04000014,%asr20,32
|
ASR20,$04,$14,%asr20,32
|
||||||
NR_ASR21,$04000015,%asr21,32
|
ASR21,$04,$15,%asr21,32
|
||||||
NR_ASR22,$04000016,%asr22,32
|
ASR22,$04,$16,%asr22,32
|
||||||
NR_ASR23,$04000017,%asr23,32
|
ASR23,$04,$17,%asr23,32
|
||||||
NR_ASR24,$04000018,%asr24,32
|
ASR24,$04,$18,%asr24,32
|
||||||
NR_ASR25,$04000019,%asr25,32
|
ASR25,$04,$19,%asr25,32
|
||||||
NR_ASR26,$0400001a,%asr26,32
|
ASR26,$04,$1a,%asr26,32
|
||||||
NR_ASR27,$0400001b,%asr27,32
|
ASR27,$04,$1b,%asr27,32
|
||||||
NR_ASR28,$0400001c,%asr28,32
|
ASR28,$04,$1c,%asr28,32
|
||||||
NR_ASR29,$0400001d,%asr29,32
|
ASR29,$04,$1d,%asr29,32
|
||||||
NR_ASR30,$0400001e,%asr30,32
|
ASR30,$04,$1e,%asr30,32
|
||||||
NR_ASR31,$0400001f,%asr31,32
|
ASR31,$04,$1f,%asr31,32
|
||||||
|
|
||||||
;
|
;
|
||||||
; $Log$
|
; $Log$
|
||||||
; Revision 1.2 2003-09-03 15:55:01 peter
|
; Revision 1.3 2003-09-03 16:29:37 peter
|
||||||
|
; * superregisters also from .dat file
|
||||||
|
;
|
||||||
|
; Revision 1.2 2003/09/03 15:55:01 peter
|
||||||
; * NEWRA branch merged
|
; * NEWRA branch merged
|
||||||
;
|
;
|
||||||
; Revision 1.1.2.2 2003/09/02 17:49:17 peter
|
; Revision 1.1.2.2 2003/09/02 17:49:17 peter
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user