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https://gitlab.com/freepascal.org/fpc/source.git
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* unarynminus and shlshr node fixed for 32bit and smaller ordinals
* small fixes in the assembler writer
* changed scratch registers, because they were used by the linker (r11
and r12) and by the abi under linux (r31)
This commit is contained in:
Jonas Maebe
parent
d8acdf44fa
commit
3e7b6ef7fa
@ -25,6 +25,8 @@
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unit agppcgas;
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{$i fpcdefs.inc}
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interface
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uses
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@ -286,7 +288,7 @@ unit agppcgas;
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else
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begin
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internalerror(2002070601);
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{ not yet implementer !!!!!!!!!!!!!!!!!!!!! }
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{ not yet implemented !!!!!!!!!!!!!!!!!!!!! }
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{ case tempstr := 'tw';}
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end;
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end;
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@ -300,9 +302,14 @@ unit agppcgas;
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begin
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op:=taicpu(hp).opcode;
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if is_calljmp(op) then
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{ direct BO/BI in op[0] and op[1] not supported, put them in condition! }
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s:=cond2str(op,taicpu(hp).condition)+
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getopstr_jmp(taicpu(hp).oper[0])
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begin
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{ direct BO/BI in op[0] and op[1] not supported, put them in condition! }
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if op <> A_B then
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s:=cond2str(op,taicpu(hp).condition)+','
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else
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s:='';
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s := s+getopstr_jmp(taicpu(hp).oper[0]);
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end
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else
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{ process operands }
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begin
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@ -330,7 +337,13 @@ begin
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end.
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{
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$Log$
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Revision 1.1 2002-07-07 09:44:31 florian
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Revision 1.2 2002-07-09 19:45:01 jonas
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* unarynminus and shlshr node fixed for 32bit and smaller ordinals
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* small fixes in the assembler writer
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* changed scratch registers, because they were used by the linker (r11
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and r12) and by the abi under linux (r31)
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Revision 1.1 2002/07/07 09:44:31 florian
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* powerpc target fixed, very simple units can be compiled
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Revision 1.6 2002/05/18 13:34:26 peter
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@ -71,6 +71,7 @@ unit cgcpu;
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l : tasmlabel);override;
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procedure a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
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procedure a_jmp_always(list : taasmoutput;l: tasmlabel); override;
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procedure a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel); override;
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procedure g_flags2reg(list: taasmoutput; const f: TResFlags; reg: TRegister); override;
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@ -320,7 +321,8 @@ const
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procedure tcgppc.a_load_reg_reg(list : taasmoutput;size : tcgsize;reg1,reg2 : tregister);
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begin
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list.concat(taicpu.op_reg_reg(A_MR,reg2,reg1));
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if (reg1 <> reg2) then
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list.concat(taicpu.op_reg_reg(A_MR,reg2,reg1));
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end;
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@ -578,6 +580,12 @@ const
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a_jmp(list,A_BC,TOpCmp2AsmCond[cond],0,l);
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end;
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procedure tcgppc.a_jmp_always(list : taasmoutput;l: tasmlabel);
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begin
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a_jmp(list,A_B,C_None,0,l);
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end;
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procedure tcgppc.a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel);
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var
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@ -853,8 +861,8 @@ const
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ref2.base,tmpref))
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else
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list.concat(taicpu.op_reg_ref(A_LIS,tmpreg,tmpref));
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ref2.base := tmpreg;
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ref2.symaddr := refs_l;
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tmpref.base := tmpreg;
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tmpref.symaddr := refs_l;
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{ can be folded with one of the next instructions by the }
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{ optimizer probably }
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list.concat(taicpu.op_reg_reg_ref(A_ADDI,tmpreg,tmpreg,tmpref));
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@ -887,6 +895,18 @@ const
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count, count2: aword;
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begin
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{ make sure short loads are handled as optimally as possible }
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if not loadref then
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if (len <= 4) and
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(byte(len) in [1,2,4]) then
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begin
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a_load_ref_ref(list,int_cgsize(len),source,dest);
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if delsource then
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reference_release(exprasmlist,source);
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exit;
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end;
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{ make sure source and dest are valid }
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src := source;
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fixref(list,src);
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@ -911,9 +931,9 @@ const
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{ the offsets are zero after the a_loadaddress_ref_reg and just }
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{ have to be set to 4. I put an Inc there so debugging may be }
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{ easier (should offset be different from zero here, it will be }
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{ easy to notice in the genreated assembler }
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Inc(dst.offset,4);
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Inc(src.offset,4);
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{ easy to notice in the generated assembler }
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inc(dst.offset,4);
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inc(src.offset,4);
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list.concat(taicpu.op_reg_reg_const(A_SUBI,src.base,src.base,4));
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list.concat(taicpu.op_reg_reg_const(A_SUBI,dst.base,dst.base,4));
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countreg := get_scratch_reg_int(list);
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@ -930,33 +950,38 @@ const
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list.concat(taicpu.op_reg_reg_const(A_SUBI,countreg,countreg,1));
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a_jmp(list,A_BC,C_NE,0,lab);
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free_scratch_reg(list,countreg);
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a_reg_dealloc(list,R_0);
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end
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else
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{ unrolled loop }
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begin
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tempreg := get_scratch_reg_int(list);
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a_reg_alloc(list,R_0);
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for count2 := 1 to count do
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begin
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a_load_ref_reg(list,OS_32,src,tempreg);
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a_load_reg_ref(list,OS_32,tempreg,dst);
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a_load_ref_reg(list,OS_32,src,R_0);
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a_load_reg_ref(list,OS_32,R_0,dst);
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inc(src.offset,4);
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inc(dst.offset,4);
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end
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end;
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a_reg_dealloc(list,R_0);
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end;
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{ copy the leftovers }
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if (len and 2) <> 0 then
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begin
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a_load_ref_reg(list,OS_16,src,tempreg);
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a_load_reg_ref(list,OS_16,tempreg,dst);
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a_reg_alloc(list,R_0);
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a_load_ref_reg(list,OS_16,src,R_0);
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a_load_reg_ref(list,OS_16,R_0,dst);
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inc(src.offset,2);
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inc(dst.offset,2);
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a_reg_dealloc(list,R_0);
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end;
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if (len and 1) <> 0 then
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begin
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a_load_ref_reg(list,OS_8,src,tempreg);
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a_load_reg_ref(list,OS_8,tempreg,dst);
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a_load_reg_ref(list,OS_16,R_0,dst);
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a_load_ref_reg(list,OS_8,src,R_0);
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a_load_reg_ref(list,OS_8,R_0,dst);
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a_reg_dealloc(list,R_0);
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end;
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a_reg_dealloc(list,tempreg);
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free_scratch_reg(list,src.base);
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free_scratch_reg(list,dst.base);
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end;
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@ -1165,7 +1190,8 @@ const
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begin
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p := taicpu.op_sym(op,newasmsymbol(l.name));
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create_cond_norm(c,crval,p.condition);
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if op <> A_B then
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create_cond_norm(c,crval,p.condition);
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p.is_jmp := true;
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list.concat(p)
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end;
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@ -1175,7 +1201,13 @@ begin
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end.
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{
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$Log$
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Revision 1.20 2002-07-07 09:44:31 florian
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Revision 1.21 2002-07-09 19:45:01 jonas
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* unarynminus and shlshr node fixed for 32bit and smaller ordinals
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* small fixes in the assembler writer
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* changed scratch registers, because they were used by the linker (r11
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and r12) and by the abi under linux (r31)
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Revision 1.20 2002/07/07 09:44:31 florian
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* powerpc target fixed, very simple units can be compiled
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Revision 1.19 2002/05/20 13:30:41 carl
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@ -463,7 +463,7 @@ uses
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routine calls or in assembler blocks.
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}
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max_scratch_regs = 3;
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scratch_regs: Array[1..max_scratch_regs] of TRegister = (R_11,R_12,R_31);
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scratch_regs: Array[1..max_scratch_regs] of TRegister = (R_28,R_29,R_30);
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{*****************************************************************************
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Default generic sizes
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@ -544,7 +544,8 @@ uses
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function is_calljmp(o:tasmop):boolean;
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procedure inverse_cond(c: TAsmCond;var r : TAsmCond);
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procedure inverse_flags(var r : TResFlags);
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procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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procedure create_cond_imm(BO,BI:byte;var r : TAsmCond);
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procedure create_cond_norm(cond: TAsmCondFlag; cr: byte;var r : TasmCond);
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@ -568,15 +569,24 @@ implementation
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end;
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end;
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procedure inverse_flags(var r: TResFlags);
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const
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inv_flags: array[F_EQ..F_GE] of TResFlagsEnum =
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(F_NE,F_EQ,F_GE,F_GE,F_LE,F_LT);
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begin
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r.flag := inv_flags[r.flag];
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end;
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procedure inverse_cond(c: TAsmCond;var r : TAsmCond);
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procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
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const
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inv_condflags:array[TAsmCondFlag] of TAsmCondFlag=(C_None,
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C_GE,C_GT,C_NE,C_LT,C_LE,C_LT,C_EQ,C_GT,C_NS,C_SO,C_NU,C_UN,
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C_F,C_T,C_DNZ,C_DNZF,C_DNZT,C_DZ,C_DZF,C_DZT);
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begin
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c.cond := inv_condflags[c.cond];
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r := c;
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r.cond := inv_condflags[c.cond];
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end;
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@ -617,7 +627,13 @@ implementation
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end.
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{
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$Log$
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Revision 1.15 2002-07-07 09:44:31 florian
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Revision 1.16 2002-07-09 19:45:01 jonas
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* unarynminus and shlshr node fixed for 32bit and smaller ordinals
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* small fixes in the assembler writer
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* changed scratch registers, because they were used by the linker (r11
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and r12) and by the abi under linux (r31)
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Revision 1.15 2002/07/07 09:44:31 florian
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* powerpc target fixed, very simple units can be compiled
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Revision 1.14 2002/05/18 13:34:26 peter
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@ -206,7 +206,7 @@ implementation
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location.registerhigh := hregisterhigh;
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hregisterlow := rg.getregisterint(exprasmlist);
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location.registerlow := hregisterlow;
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tcg64f32(cg).a_load64_ref_reg(exprasmlist,
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cg64.a_load64_ref_reg(exprasmlist,
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left.location.reference,joinreg64(hregisterlow,hregisterhigh));
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end;
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end;
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@ -315,25 +315,17 @@ implementation
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else
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begin
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{ load left operators in a register }
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if (left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER) then
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begin
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reference_release(exprasmlist,left.location.reference);
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hregister1 := rg.getregisterint(exprasmlist);
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{ OS_32 because everything is always converted to longint/ }
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{ cardinal in the resulttype pass (JM) }
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cg.a_load_ref_reg(exprasmlist,OS_32,left.location.reference,
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hregister1);
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resultreg := hregister1;
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end
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else
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begin
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hregister1 := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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resultreg := rg.getregisterint(exprasmlist)
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else
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resultreg := hregister1;
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location.loc := LOC_REGISTER;
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resultreg := rg.getregisterint(exprasmlist);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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@ -347,29 +339,14 @@ implementation
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else
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begin
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{ load shift count in a register if necessary }
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case right.location.loc of
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LOC_CREGISTER, LOC_REGISTER:
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hregister2 := right.location.register;
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LOC_REFERENCE, LOC_CREFERENCE:
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begin
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hregister2 := cg.get_scratch_reg_int(exprasmlist);
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cg.a_load_ref_reg(exprasmlist,OS_32,
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right.location.reference,hregister2);
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reference_release(exprasmlist,right.location.reference);
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end;
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end;
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location_force_reg(exprasmlist,right.location,def_cgsize(right.resulttype.def),true);
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hregister2 := right.location.register;
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tcgppc(cg).a_op_reg_reg_reg(exprasmlist,op,OS_32,hregister1,
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hregister2,resultreg);
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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cg.free_scratch_reg(exprasmlist,hregister2)
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else
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rg.ungetregister(exprasmlist,hregister2);
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rg.ungetregister(exprasmlist,hregister2);
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end;
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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end;
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end;
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@ -391,8 +368,8 @@ implementation
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
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location_copy(location,left.location);
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exprasmlist.concat(taicpu.op_reg_reg(A_NEG,location.registerlow,
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src1));
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cg.a_op_reg_reg(exprasmlist,OP_NOT,OS_32,src2,location.registerhigh);
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location.registerlow));
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cg.a_op_reg_reg(exprasmlist,OP_NOT,OS_32,location.registerhigh,location.registerhigh);
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tmp := cg.get_scratch_reg_int(exprasmlist);
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cg.a_op_const_reg_reg(exprasmlist,OP_SAR,OS_32,31,location.registerlow,
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tmp);
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@ -406,6 +383,7 @@ implementation
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end
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else
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begin
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location_copy(location,left.location);
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location.loc:=LOC_REGISTER;
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case left.location.loc of
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LOC_FPUREGISTER, LOC_REGISTER:
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@ -495,26 +473,18 @@ implementation
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end;
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LOC_FLAGS :
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begin
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location.resflags:=left.location.resflags;
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{$warning !!!}
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// inverse_flags(left.location.resflags);
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE :
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begin
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if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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regl := left.location.register
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else
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begin
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regl := rg.getregisterint(exprasmlist);
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cg.a_load_ref_reg(exprasmlist,def_cgsize(left.resulttype.def),
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left.location.reference,regl);
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end;
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location.loc:=LOC_FLAGS;
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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exprasmlist.concat(taicpu.op_reg_const(A_CMPWI,left.location.register,0));
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location_release(exprasmlist,left.location);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags.cr:=r_cr0;
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location.resflags.flag:=F_EQ;
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exprasmlist.concat(taicpu.op_reg_const(A_CMPWI,regl,0));
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rg.ungetregister(exprasmlist,regl);
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end;
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end;
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end;
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end
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else if is_64bitint(left.resulttype.def) then
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@ -524,9 +494,9 @@ implementation
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location_copy(location,left.location);
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{ perform the NOT operation }
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exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerhigh,
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regh));
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location.registerhigh));
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exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerlow,
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regl));
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location.registerlow));
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end
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else
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begin
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@ -549,7 +519,13 @@ begin
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end.
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{
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$Log$
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Revision 1.11 2002-07-07 09:44:32 florian
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Revision 1.12 2002-07-09 19:45:01 jonas
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* unarynminus and shlshr node fixed for 32bit and smaller ordinals
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* small fixes in the assembler writer
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* changed scratch registers, because they were used by the linker (r11
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and r12) and by the abi under linux (r31)
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Revision 1.11 2002/07/07 09:44:32 florian
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* powerpc target fixed, very simple units can be compiled
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Revision 1.10 2002/05/20 13:30:42 carl
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