diff --git a/.gitattributes b/.gitattributes
index 28b7c55fe1..38317f4b8c 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -7426,8 +7426,10 @@ rtl/embedded/Makefile svneol=native#text/plain
rtl/embedded/Makefile.fpc svneol=native#text/plain
rtl/embedded/arm/at91sam7x256.pp svneol=native#text/plain
rtl/embedded/arm/cortexm3_start.inc svneol=native#text/pascal
+rtl/embedded/arm/cortexm4f_start.inc svneol=native#text/pascal
rtl/embedded/arm/lm3fury.pp svneol=native#text/pascal
rtl/embedded/arm/lm3tempest.pp svneol=native#text/pascal
+rtl/embedded/arm/lm4f120.pp svneol=native#text/pascal
rtl/embedded/arm/lpc1768.pp svneol=native#text/pascal
rtl/embedded/arm/lpc21x4.pp svneol=native#text/plain
rtl/embedded/arm/sc32442b.pp svneol=native#text/pascal
diff --git a/compiler/arm/agarmgas.pas b/compiler/arm/agarmgas.pas
index f59a6a071c..98439bbcca 100644
--- a/compiler/arm/agarmgas.pas
+++ b/compiler/arm/agarmgas.pas
@@ -109,8 +109,8 @@ unit agarmgas;
if (current_settings.fputype = fpu_fpv4_s16) then
result:='-mfpu=fpv4-sp-d16 '+result;
- if current_settings.cputype=cpu_armv7m then
- result:='-march=armv7m -mthumb -mthumb-interwork '+result
+ if current_settings.cputype in cpu_thumb2 then
+ result:='-march='+cputype_to_gas_march[current_settings.cputype]+' -mthumb -mthumb-interwork '+result
// EDSP instructions in RTL require armv5te at least to not generate error
else if current_settings.cputype >= cpu_armv5te then
result:='-march='+cputype_to_gas_march[current_settings.cputype]+' '+result;
diff --git a/compiler/arm/cpuinfo.pas b/compiler/arm/cpuinfo.pas
index e918717890..680d70282c 100644
--- a/compiler/arm/cpuinfo.pas
+++ b/compiler/arm/cpuinfo.pas
@@ -53,7 +53,7 @@ Type
Const
cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
cpu_thumb = [];
- cpu_thumb2 = [cpu_armv7m];
+ cpu_thumb2 = [cpu_armv7m,cpu_armv7em];
Type
tfputype =
@@ -196,6 +196,9 @@ Type
ct_lm3s9b95,
ct_lm3s9b96,
+ { TI Stellaris }
+ ct_lm4f120h5,
+
{ SAMSUNG }
ct_sc32442b,
@@ -1020,6 +1023,16 @@ Const
sramsize:$00010000
),
+ // ct_lm4f120h5,
+ (
+ controllertypestr:'LM4F120H5';
+ controllerunitstr:'LM4F120';
+ flashbase:$00000000;
+ flashsize:$00040000;
+ srambase:$20000000;
+ sramsize:$00008000
+ ),
+
//ct_SC32442b,
(
controllertypestr:'SC32442B';
@@ -1067,6 +1080,7 @@ Const
CPUARM_HAS_EDSP, { CPU supports the PLD,STRD,LDRD,MCRR and MRRC instructions }
CPUARM_HAS_REV, { CPU supports the REV instruction }
CPUARM_HAS_RBIT, { CPU supports the RBIT instruction }
+ CPUARM_HAS_DMB, { CPU has memory barrier instructions (DMB, DSB, ISB) }
CPUARM_HAS_LDREX,
CPUARM_HAS_IDIV
);
@@ -1086,11 +1100,11 @@ Const
{ cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
{ cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
{ the identifier armv7 is should not be used, it is considered being equal to armv7a }
- { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
- { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
- { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
- { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
- { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
+ { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
+ { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
+ { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
+ { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB],
+ { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB]
);
Implementation
diff --git a/compiler/arm/narmmat.pas b/compiler/arm/narmmat.pas
index 150105f3c8..5734811baa 100644
--- a/compiler/arm/narmmat.pas
+++ b/compiler/arm/narmmat.pas
@@ -79,11 +79,11 @@ implementation
) and
not(is_64bitint(resultdef)) then
result:=nil
- else if (current_settings.cputype in [cpu_armv7m]) and
+ else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
(nodetype=divn) and
not(is_64bitint(resultdef)) then
result:=nil
- else if (current_settings.cputype in [cpu_armv7m]) and
+ else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
(nodetype=modn) and
not(is_64bitint(resultdef)) then
begin
@@ -198,7 +198,7 @@ implementation
secondpass(left);
secondpass(right);
- if (current_settings.cputype in [cpu_armv7m]) and
+ if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
(nodetype=divn) and
not(is_64bitint(resultdef)) then
begin
diff --git a/compiler/systems/t_embed.pas b/compiler/systems/t_embed.pas
index 18a90c1a43..af7f62d974 100644
--- a/compiler/systems/t_embed.pas
+++ b/compiler/systems/t_embed.pas
@@ -337,6 +337,10 @@ begin
ct_lm3s9b92,
ct_lm3s9b95,
ct_lm3s9b96,
+
+ { TI - Stellaris something }
+ ct_lm4f120h5,
+
ct_sc32442b,
ct_thumb2bare:
begin
diff --git a/rtl/arm/setjump.inc b/rtl/arm/setjump.inc
index 79a62d55d8..fb7ecbcda0 100644
--- a/rtl/arm/setjump.inc
+++ b/rtl/arm/setjump.inc
@@ -27,7 +27,7 @@ function fpc_setjmp(var S : jmp_buf) : longint;assembler;[Public, alias : 'FPC_S
{$endif}
{$endif}
- {$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
+ {$if defined(CPUARMV7EM) or defined(CPUARMV7M)}
stmia r0!, {v1-v6, sl, fp}
mov r2, sp
stmia r0!, {r2, lr}
@@ -44,7 +44,7 @@ function fpc_setjmp(var S : jmp_buf) : longint;assembler;[Public, alias : 'FPC_S
procedure fpc_longjmp(var S : jmp_buf;value : longint);assembler;[Public, alias : 'FPC_LONGJMP']; compilerproc;
asm
- {$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
+ {$if defined(CPUARMV7EM) or defined(CPUARMV7M)}
mov ip, r0
movs r0, r1
it eq
diff --git a/rtl/arm/thumb2.inc b/rtl/arm/thumb2.inc
index ce3cfa5db3..f75add7504 100644
--- a/rtl/arm/thumb2.inc
+++ b/rtl/arm/thumb2.inc
@@ -39,7 +39,6 @@ begin
ldr r1, [r0]
orr r1, r1, #(0xF << 20)
str r1, [r0]
- bx lr
{$ELSE FPUFPV4_S16}
rfs r0
and r0,r0,#0xffe0ffff
diff --git a/rtl/embedded/Makefile b/rtl/embedded/Makefile
index 267dfa6fd2..032ed92a1e 100644
--- a/rtl/embedded/Makefile
+++ b/rtl/embedded/Makefile
@@ -1,5 +1,5 @@
#
-# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/09/26]
+# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/10/12]
#
default: all
MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-qnx i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim m68k-linux m68k-freebsd m68k-netbsd m68k-amiga m68k-atari m68k-openbsd m68k-palmos m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macos powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded arm-linux arm-palmos arm-darwin arm-wince arm-gba arm-nds arm-embedded arm-symbian powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux jvm-java jvm-android
@@ -319,7 +319,10 @@ CPU_UNITS=
SYSINIT_UNITS=
ifeq ($(ARCH),arm)
ifeq ($(SUBARCH),armv7m)
-CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
+CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 lm4f120 # thumb2_bare
+endif
+ifeq ($(SUBARCH),armv7em)
+CPU_UNITS=lm4f120 # thumb2_bare
endif
ifeq ($(SUBARCH),armv4t)
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
diff --git a/rtl/embedded/Makefile.fpc b/rtl/embedded/Makefile.fpc
index 20890e12ce..408a247eeb 100644
--- a/rtl/embedded/Makefile.fpc
+++ b/rtl/embedded/Makefile.fpc
@@ -49,7 +49,10 @@ SYSINIT_UNITS=
ifeq ($(ARCH),arm)
ifeq ($(SUBARCH),armv7m)
-CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
+CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 lm4f120 # thumb2_bare
+endif
+ifeq ($(SUBARCH),armv7em)
+CPU_UNITS=lm4f120 # thumb2_bare
endif
ifeq ($(SUBARCH),armv4t)
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
diff --git a/rtl/embedded/arm/cortexm4f_start.inc b/rtl/embedded/arm/cortexm4f_start.inc
new file mode 100644
index 0000000000..415aab73dd
--- /dev/null
+++ b/rtl/embedded/arm/cortexm4f_start.inc
@@ -0,0 +1,52 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+ b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+ ldr r1,.L_etext
+ ldr r2,.L_data
+ ldr r3,.L_edata
+.Lcopyloop:
+ cmp r2,r3
+ ittt ls
+ ldrls r0,[r1],#4
+ strls r0,[r2],#4
+ bls .Lcopyloop
+
+ // clear onboard ram
+ ldr r1,.L_bss_start
+ ldr r2,.L_bss_end
+ mov r0,#0
+.Lzeroloop:
+ cmp r1,r2
+ itt ls
+ strls r0,[r1],#4
+ bls .Lzeroloop
+
+ bl PASCALMAIN
+ b HaltProc
+
+.L_bss_start:
+ .long _bss_start
+.L_bss_end:
+ .long _bss_end
+.L_etext:
+ .long _etext
+.L_data:
+ .long _data
+.L_edata:
+ .long _edata
+end;
\ No newline at end of file
diff --git a/rtl/embedded/arm/lm4f120.pp b/rtl/embedded/arm/lm4f120.pp
new file mode 100644
index 0000000000..ee922ffec5
--- /dev/null
+++ b/rtl/embedded/arm/lm4f120.pp
@@ -0,0 +1,443 @@
+{$goto on}
+unit lm4f120;
+
+interface
+
+const
+ Flash_Base = $00000000;
+ ROM_Base = $01000000;
+ SRAM_Base = $20000000;
+ Bitband_Base = $22000000;
+
+ // FiRM Peripherals
+ Watchdog0_Base = $40000000;
+ Watchdog1_Base = $40001000;
+ GPIOA_Base = $40004000;
+ GPIOB_Base = $40005000;
+ GPIOC_Base = $40006000;
+ GPIOD_Base = $40007000;
+ SSI0_Base = $40008000;
+ SSI1_Base = $40009000;
+ SSI2_Base = $4000A000;
+ SSI3_Base = $4000B000;
+ UART0_Base = $4000C000;
+ UART1_Base = $4000D000;
+ UART2_Base = $4000E000;
+ UART3_Base = $4000F000;
+ UART4_Base = $40010000;
+ UART5_Base = $40011000;
+ UART6_Base = $40012000;
+ UART7_Base = $40013000;
+
+ // Peripherals
+ I2C0_Base = $40020000;
+ I2C1_Base = $40021000;
+ I2C2_Base = $40022000;
+ I2C3_Base = $40023000;
+ GPIOE_Base = $40024000;
+ GPIOF_Base = $40025000;
+ Timer0_1632_Base = $40030000;
+ Timer1_1632_Base = $40031000;
+ Timer2_1632_Base = $40032000;
+ Timer3_1632_Base = $40033000;
+ Timer4_1632_Base = $40034000;
+ Timer5_1632_Base = $40035000;
+ Timer0_3264_Base = $40036000;
+ Timer1_3264_Base = $40037000;
+ ADC0_Base = $40038000;
+ ADC1_Base = $40039000;
+ AnalogComp_Base = $4003C000;
+ CAN0_Base = $40040000;
+ Timer2_3264_Base = $4004C000;
+ Timer3_3264_Base = $4004D000;
+ Timer4_3264_Base = $4004E000;
+ Timer5_3264_Base = $4004F000;
+ USB_Base = $40050000;
+ GPIOA_AHB_Base = $40058000;
+ GPIOB_AHB_Base = $40059000;
+ GPIOC_AHB_Base = $4005A000;
+ GPIOD_AHB_Base = $4005B000;
+ GPIOE_AHB_Base = $4005C000;
+ GPIOF_AHB_Base = $4005D000;
+ EEPROMKeyLocker_Base = $400AF000;
+ SystemException_Base = $400F9000;
+ Hibernation_Base = $400FC000;
+ FlashControl_Base = $400FD000;
+ SystemControl_Base = $400FE000;
+ uDMA_Base = $400FF000;
+ PeriphBitband_Base = $42000000;
+// Private Peripheral Bus
+ ITM_Base = $E0000000;
+ DWT_Base = $E0001000;
+ FPB_Base = $E0002000;
+ CortexM4F_Base = $E000E000;
+ TPIU_Base = $E0040000;
+ ETM_Base = $E0041000;
+
+implementation
+
+procedure NMI_interrupt; external name 'NMI_interrupt';
+procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
+procedure MemManage_interrupt; external name 'MemManage_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SWI_interrupt; external name 'SWI_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+
+procedure GPIO_Port_A_interrupt; external name 'GPIO_Port_A_interrupt';
+procedure GPIO_Port_B_interrupt; external name 'GPIO_Port_B_interrupt';
+procedure GPIO_Port_C_interrupt; external name 'GPIO_Port_C_interrupt';
+procedure GPIO_Port_D_interrupt; external name 'GPIO_Port_D_interrupt';
+procedure GPIO_Port_E_interrupt; external name 'GPIO_Port_E_interrupt';
+procedure UART0_interrupt; external name 'UART0_interrupt';
+procedure UART1_interrupt; external name 'UART1_interrupt';
+procedure SSI0_interrupt; external name 'SSI0_interrupt';
+procedure I2C0_interrupt; external name 'I2C0_interrupt';
+procedure ADC0_Seq_0_interrupt; external name 'ADC0_Seq_0_interrupt';
+procedure ADC0_Seq_1_interrupt; external name 'ADC0_Seq_1_interrupt';
+procedure ADC0_Seq_2_interrupt; external name 'ADC0_Seq_2_interrupt';
+procedure ADC0_Seq_3_interrupt; external name 'ADC0_Seq_3_interrupt';
+procedure Watchdog_0_and_1_interrupt; external name 'Watchdog_0_and_1_interrupt';
+procedure Timer_1632_0A_interrupt; external name 'Timer_1632_0A_interrupt';
+procedure Timer_1632_0B_interrupt; external name 'Timer_1632_0B_interrupt';
+procedure Timer_1632_1A_interrupt; external name 'Timer_1632_1A_interrupt';
+procedure Timer_1632_1B_interrupt; external name 'Timer_1632_1B_interrupt';
+procedure Timer_1632_2A_interrupt; external name 'Timer_1632_2A_interrupt';
+procedure Timer_1632_2B_interrupt; external name 'Timer_1632_2B_interrupt';
+procedure Analog_Comp_0_interrupt; external name 'Analog_Comp_0_interrupt';
+procedure Analog_Comp_1_interrupt; external name 'Analog_Comp_1_interrupt';
+procedure System_Control_interrupt; external name 'System_Control_interrupt';
+procedure Flash_and_EEPROM_interrupt; external name 'Flash_and_EEPROM_interrupt';
+procedure GPIO_Port_F_interrupt; external name 'GPIO_Port_F_interrupt';
+procedure UART2_interrupt; external name 'UART2_interrupt';
+procedure SSI1_interrupt; external name 'SSI1_interrupt';
+procedure Timer_1632_3A_interrupt; external name 'Timer_1632_3A_interrupt';
+procedure Timer_1632_3B_interrupt; external name 'Timer_1632_3B_interrupt';
+procedure I2C1_interrupt; external name 'I2C1_interrupt';
+procedure CAN0_interrupt; external name 'CAN0_interrupt';
+procedure Hibernation_interrupt; external name 'Hibernation_interrupt';
+procedure USB_interrupt; external name 'USB_interrupt';
+procedure uDMA_Software_interrupt; external name 'uDMA_Software_interrupt';
+procedure uDMA_Error_interrupt; external name 'uDMA_Error_interrupt';
+procedure ADC1_Seq_0_interrupt; external name 'ADC1_Seq_0_interrupt';
+procedure ADC1_Seq_1_interrupt; external name 'ADC1_Seq_1_interrupt';
+procedure ADC1_Seq_2_interrupt; external name 'ADC1_Seq_2_interrupt';
+procedure ADC1_Seq_3_interrupt; external name 'ADC1_Seq_3_interrupt';
+procedure SSI2_interrupt; external name 'SSI2_interrupt';
+procedure SSI3_interrupt; external name 'SSI3_interrupt';
+procedure UART3_interrupt; external name 'UART3_interrupt';
+procedure UART4_interrupt; external name 'UART4_interrupt';
+procedure UART5_interrupt; external name 'UART5_interrupt';
+procedure UART6_interrupt; external name 'UART6_interrupt';
+procedure UART7_interrupt; external name 'UART7_interrupt';
+procedure I2C2_interrupt; external name 'I2C2_interrupt';
+procedure I2C3_interrupt; external name 'I2C3_interrupt';
+procedure Timer_1632_4A_interrupt; external name 'Timer_1632_4A_interrupt';
+procedure Timer_1632_4B_interrupt; external name 'Timer_1632_4B_interrupt';
+procedure Timer_1632_5A_interrupt; external name 'Timer_1632_5A_interrupt';
+procedure Timer_1632_5B_interrupt; external name 'Timer_1632_5B_interrupt';
+procedure Timer_3264_0A_interrupt; external name 'Timer_3264_0A_interrupt';
+procedure Timer_3264_0B_interrupt; external name 'Timer_3264_0B_interrupt';
+procedure Timer_3264_1A_interrupt; external name 'Timer_3264_1A_interrupt';
+procedure Timer_3264_1B_interrupt; external name 'Timer_3264_1B_interrupt';
+procedure Timer_3264_2A_interrupt; external name 'Timer_3264_2A_interrupt';
+procedure Timer_3264_2B_interrupt; external name 'Timer_3264_2B_interrupt';
+procedure Timer_3264_3A_interrupt; external name 'Timer_3264_3A_interrupt';
+procedure Timer_3264_3B_interrupt; external name 'Timer_3264_3B_interrupt';
+procedure Timer_3264_4A_interrupt; external name 'Timer_3264_4A_interrupt';
+procedure Timer_3264_4B_interrupt; external name 'Timer_3264_4B_interrupt';
+procedure Timer_3264_5A_interrupt; external name 'Timer_3264_5A_interrupt';
+procedure Timer_3264_5B_interrupt; external name 'Timer_3264_5B_interrupt';
+procedure System_Exception_imprecise_interrupt; external name 'System_Exception_imprecise_interrupt';
+
+{$i cortexm4f_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+ .section ".init.interrupt_vectors"
+interrupt_vectors:
+ .long _stack_top
+ .long Startup
+ .long NMI_interrupt
+ .long Hardfault_interrupt
+ .long MemManage_interrupt
+ .long BusFault_interrupt
+ .long UsageFault_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SWI_interrupt
+ .long DebugMonitor_interrupt
+ .long 0
+ .long PendingSV_interrupt
+ .long SysTick_interrupt
+
+ .long GPIO_Port_A_interrupt
+ .long GPIO_Port_B_interrupt
+ .long GPIO_Port_C_interrupt
+ .long GPIO_Port_D_interrupt
+ .long GPIO_Port_E_interrupt
+ .long UART0_interrupt
+ .long UART1_interrupt
+ .long SSI0_interrupt
+ .long I2C0_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long ADC0_Seq_0_interrupt
+ .long ADC0_Seq_1_interrupt
+ .long ADC0_Seq_2_interrupt
+ .long ADC0_Seq_3_interrupt
+ .long Watchdog_0_and_1_interrupt
+ .long Timer_1632_0A_interrupt
+ .long Timer_1632_0B_interrupt
+ .long Timer_1632_1A_interrupt
+ .long Timer_1632_1B_interrupt
+ .long Timer_1632_2A_interrupt
+ .long Timer_1632_2B_interrupt
+ .long Analog_Comp_0_interrupt
+ .long 0
+ .long Analog_Comp_1_interrupt
+ .long System_Control_interrupt
+ .long Flash_and_EEPROM_interrupt
+ .long GPIO_Port_F_interrupt
+ .long 0
+ .long 0
+ .long UART2_interrupt
+ .long SSI1_interrupt
+ .long Timer_1632_3A_interrupt
+ .long Timer_1632_3B_interrupt
+ .long I2C1_interrupt
+ .long 0
+ .long CAN0_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long Hibernation_interrupt
+ .long USB_interrupt
+ .long 0
+ .long uDMA_Software_interrupt
+ .long uDMA_Error_interrupt
+ .long ADC1_Seq_0_interrupt
+ .long ADC1_Seq_1_interrupt
+ .long ADC1_Seq_2_interrupt
+ .long ADC1_Seq_3_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SSI2_interrupt
+ .long SSI3_interrupt
+ .long UART3_interrupt
+ .long UART4_interrupt
+ .long UART5_interrupt
+ .long UART6_interrupt
+ .long UART7_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long I2C2_interrupt
+ .long I2C3_interrupt
+ .long Timer_1632_4A_interrupt
+ .long Timer_1632_4B_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long Timer_1632_5A_interrupt
+ .long Timer_1632_5B_interrupt
+ .long Timer_3264_0A_interrupt
+ .long Timer_3264_0B_interrupt
+ .long Timer_3264_1A_interrupt
+ .long Timer_3264_1B_interrupt
+ .long Timer_3264_2A_interrupt
+ .long Timer_3264_2B_interrupt
+ .long Timer_3264_3A_interrupt
+ .long Timer_3264_3B_interrupt
+ .long Timer_3264_4A_interrupt
+ .long Timer_3264_4B_interrupt
+ .long Timer_3264_5A_interrupt
+ .long Timer_3264_5B_interrupt
+ .long System_Exception_imprecise_interrupt
+
+ .weak NMI_interrupt
+ .weak Hardfault_interrupt
+ .weak MemManage_interrupt
+ .weak BusFault_interrupt
+ .weak UsageFault_interrupt
+ .weak SWI_interrupt
+ .weak DebugMonitor_interrupt
+ .weak PendingSV_interrupt
+ .weak SysTick_interrupt
+
+ .weak GPIO_Port_A_interrupt
+ .weak GPIO_Port_B_interrupt
+ .weak GPIO_Port_C_interrupt
+ .weak GPIO_Port_D_interrupt
+ .weak GPIO_Port_E_interrupt
+ .weak UART0_interrupt
+ .weak UART1_interrupt
+ .weak SSI0_interrupt
+ .weak I2C0_interrupt
+ .weak ADC0_Seq_0_interrupt
+ .weak ADC0_Seq_1_interrupt
+ .weak ADC0_Seq_2_interrupt
+ .weak ADC0_Seq_3_interrupt
+ .weak Watchdog_0_and_1_interrupt
+ .weak Timer_1632_0A_interrupt
+ .weak Timer_1632_0B_interrupt
+ .weak Timer_1632_1A_interrupt
+ .weak Timer_1632_1B_interrupt
+ .weak Timer_1632_2A_interrupt
+ .weak Timer_1632_2B_interrupt
+ .weak Analog_Comp_0_interrupt
+ .weak Analog_Comp_1_interrupt
+ .weak System_Control_interrupt
+ .weak Flash_and_EEPROM_interrupt
+ .weak GPIO_Port_F_interrupt
+ .weak UART2_interrupt
+ .weak SSI1_interrupt
+ .weak Timer_1632_3A_interrupt
+ .weak Timer_1632_3B_interrupt
+ .weak I2C1_interrupt
+ .weak CAN0_interrupt
+ .weak Hibernation_interrupt
+ .weak USB_interrupt
+ .weak uDMA_Software_interrupt
+ .weak uDMA_Error_interrupt
+ .weak ADC1_Seq_0_interrupt
+ .weak ADC1_Seq_1_interrupt
+ .weak ADC1_Seq_2_interrupt
+ .weak ADC1_Seq_3_interrupt
+ .weak SSI2_interrupt
+ .weak SSI3_interrupt
+ .weak UART3_interrupt
+ .weak UART4_interrupt
+ .weak UART5_interrupt
+ .weak UART6_interrupt
+ .weak UART7_interrupt
+ .weak I2C2_interrupt
+ .weak I2C3_interrupt
+ .weak Timer_1632_4A_interrupt
+ .weak Timer_1632_4B_interrupt
+ .weak Timer_1632_5A_interrupt
+ .weak Timer_1632_5B_interrupt
+ .weak Timer_3264_0A_interrupt
+ .weak Timer_3264_0B_interrupt
+ .weak Timer_3264_1A_interrupt
+ .weak Timer_3264_1B_interrupt
+ .weak Timer_3264_2A_interrupt
+ .weak Timer_3264_2B_interrupt
+ .weak Timer_3264_3A_interrupt
+ .weak Timer_3264_3B_interrupt
+ .weak Timer_3264_4A_interrupt
+ .weak Timer_3264_4B_interrupt
+ .weak Timer_3264_5A_interrupt
+ .weak Timer_3264_5B_interrupt
+ .weak System_Exception_imprecise_interrupt
+
+ .set NMI_interrupt, Startup
+ .set Hardfault_interrupt, Startup
+ .set MemManage_interrupt, Startup
+ .set BusFault_interrupt, Startup
+ .set UsageFault_interrupt, Startup
+ .set SWI_interrupt, Startup
+ .set DebugMonitor_interrupt, Startup
+ .set PendingSV_interrupt, Startup
+ .set SysTick_interrupt, Startup
+
+ .set GPIO_Port_A_interrupt, Startup
+ .set GPIO_Port_B_interrupt, Startup
+ .set GPIO_Port_C_interrupt, Startup
+ .set GPIO_Port_D_interrupt, Startup
+ .set GPIO_Port_E_interrupt, Startup
+ .set UART0_interrupt, Startup
+ .set UART1_interrupt, Startup
+ .set SSI0_interrupt, Startup
+ .set I2C0_interrupt, Startup
+ .set ADC0_Seq_0_interrupt, Startup
+ .set ADC0_Seq_1_interrupt, Startup
+ .set ADC0_Seq_2_interrupt, Startup
+ .set ADC0_Seq_3_interrupt, Startup
+ .set Watchdog_0_and_1_interrupt, Startup
+ .set Timer_1632_0A_interrupt, Startup
+ .set Timer_1632_0B_interrupt, Startup
+ .set Timer_1632_1A_interrupt, Startup
+ .set Timer_1632_1B_interrupt, Startup
+ .set Timer_1632_2A_interrupt, Startup
+ .set Timer_1632_2B_interrupt, Startup
+ .set Analog_Comp_0_interrupt, Startup
+ .set Analog_Comp_1_interrupt, Startup
+ .set System_Control_interrupt, Startup
+ .set Flash_and_EEPROM_interrupt, Startup
+ .set GPIO_Port_F_interrupt, Startup
+ .set UART2_interrupt, Startup
+ .set SSI1_interrupt, Startup
+ .set Timer_1632_3A_interrupt, Startup
+ .set Timer_1632_3B_interrupt, Startup
+ .set I2C1_interrupt, Startup
+ .set CAN0_interrupt, Startup
+ .set Hibernation_interrupt, Startup
+ .set USB_interrupt, Startup
+ .set uDMA_Software_interrupt, Startup
+ .set uDMA_Error_interrupt, Startup
+ .set ADC1_Seq_0_interrupt, Startup
+ .set ADC1_Seq_1_interrupt, Startup
+ .set ADC1_Seq_2_interrupt, Startup
+ .set ADC1_Seq_3_interrupt, Startup
+ .set SSI2_interrupt, Startup
+ .set SSI3_interrupt, Startup
+ .set UART3_interrupt, Startup
+ .set UART4_interrupt, Startup
+ .set UART5_interrupt, Startup
+ .set UART6_interrupt, Startup
+ .set UART7_interrupt, Startup
+ .set I2C2_interrupt, Startup
+ .set I2C3_interrupt, Startup
+ .set Timer_1632_4A_interrupt, Startup
+ .set Timer_1632_4B_interrupt, Startup
+ .set Timer_1632_5A_interrupt, Startup
+ .set Timer_1632_5B_interrupt, Startup
+ .set Timer_3264_0A_interrupt, Startup
+ .set Timer_3264_0B_interrupt, Startup
+ .set Timer_3264_1A_interrupt, Startup
+ .set Timer_3264_1B_interrupt, Startup
+ .set Timer_3264_2A_interrupt, Startup
+ .set Timer_3264_2B_interrupt, Startup
+ .set Timer_3264_3A_interrupt, Startup
+ .set Timer_3264_3B_interrupt, Startup
+ .set Timer_3264_4A_interrupt, Startup
+ .set Timer_3264_4B_interrupt, Startup
+ .set Timer_3264_5A_interrupt, Startup
+ .set Timer_3264_5B_interrupt, Startup
+ .set System_Exception_imprecise_interrupt, Startup
+
+ .text
+end;
+
+end.
+
diff --git a/rtl/inc/system.inc b/rtl/inc/system.inc
index b53d92cf51..6cbc093dfa 100644
--- a/rtl/inc/system.inc
+++ b/rtl/inc/system.inc
@@ -218,7 +218,7 @@ function do_isdevice(handle:thandle):boolean;forward;
{$Error Can't determine processor type !}
{$endif}
{$i armdefines.inc}
- {$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
+ {$if defined(CPUARMV7EM) or defined(CPUARMV7M)}
{$i thumb2.inc} { Case dependent, don't change }
{$else}
{$i arm.inc} { Case dependent, don't change }
diff --git a/rtl/java/jsystem.inc b/rtl/java/jsystem.inc
index 711c6f7fab..9a2817dd5f 100644
--- a/rtl/java/jsystem.inc
+++ b/rtl/java/jsystem.inc
@@ -226,7 +226,7 @@ function do_isdevice(handle:thandle):boolean;forward;
{$Error Can't determine processor type !}
{$endif}
{$i armdefines.inc}
- {$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
+ {$if defined(CPUARMV7EM) or defined(CPUARMV7M)}
{$i thumb2.inc} { Case dependent, don't change }
{$else}
{$i arm.inc} { Case dependent, don't change }