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* fixed basic signal handling for PowerPC64/linux, by updating related types and major code cleanup
git-svn-id: trunk@1364 -
This commit is contained in:
tom_at_work
parent
0b34b01a6d
commit
3f4682400c
@ -19,43 +19,78 @@
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procedure SignalToRunerror(sig : longint; SigInfo: PSigInfo; SigContext: PSigContext);cdecl;
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var
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res : word;
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{ fpustate: longint; }
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fpustate : qword;
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{$IFDEF EXCDEBUG}
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p : pbyte;
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i, j : integer;
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{$ENDIF}
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begin
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res:=0;
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{$IFDEF EXCDEBUG}
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writeln('signaltorunerror');
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{ dump SigContext }
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p := pbyte(SigContext);
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for j := 0 to sizeof(TSigContext) div 8 do begin
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for i := 0 to 7 do begin
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write(hexstr(p^, 2));
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inc(p);
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end;
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write(' ');
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end;
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writeln;
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{$ENDIF}
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{ SigContext is actally a pointer to a ucontext structure.
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So we do some ugly pointer casting to get it right again.
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See also in the *kernel* sources arch/ppc64/kernel/signal.c,
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function setup_rt_sigframe() }
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SigContext := @(PUContext(SigContext)^.uc_mcontext);
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{ exception flags are turned off by kernel }
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fpc_enable_ppc_fpu_exceptions;
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case sig of
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SIGFPE :
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begin
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{
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fpscr is cleared by the kernel -> can't find out cause :(
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fpustate := fpc_get_ppc_fpscr;
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if (fpustate and ppc_fpu_underflow) <> 0 then
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res := 206
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else if (fpustate and ppc_fpu_overflow) <> 0 then
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res := 205
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else if (fpustate and ppc_fpu_divbyzero) <> 0 then
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res := 200
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else
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}
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res := 207;
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end;
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begin
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{ ugly typecast to get the FPSCR register contents }
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fpustate := QWord(PQWord(@SigContext^.fp_regs[PT_FPSCR])^);
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{$IFDEF EXCDEBUG}
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writeln('fpustate = ', hexstr(fpustate, sizeof(fpustate)*2));
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{$ENDIF}
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{ TODO: distinguishing FPU signal type does not work as it should
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if (fpustate and ppc_fpu_underflow) <> 0 then
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res := 206
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else if (fpustate and ppc_fpu_overflow) <> 0 then
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res := 205
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else if (fpustate and ppc_fpu_divbyzero) <> 0 then
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res := 200
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else }
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res := 207;
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end;
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SIGBUS :
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res:=214;
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res:=214;
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SIGILL,
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SIGSEGV :
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res:=216;
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res:=216;
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end;
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{$IFDEF EXCDEBUG}
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writeln('sig = ', sig);
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writeln('siginfo = ', hexstr(ptrint(siginfo), sizeof(siginfo)*2));
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writeln('sigcontext = ', hexstr(ptrint(sigcontext), sizeof(sigcontext)*2));
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writeln('sigcontext...signal = ', hexstr(sigcontext^.signal, 16));
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writeln('sigcontext^...regs = ', hexstr(ptrint(sigcontext^.regs), 16));
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{$ENDIF}
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reenable_signal(sig);
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{ give runtime error at the position where the signal was raised }
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if res<>0 then
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HandleErrorAddrFrame(res,pointer(SigContext^.pt_regs^.nip),pointer(SigContext^.pt_regs^.gpr[1]));
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HandleErrorAddrFrame(res, pointer(SigContext^.gp_regs[PT_NIP]), pointer(SigContext^.gp_regs[PT_R1]));
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{$IFDEF EXCDEBUG}
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readln;
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{$ENDIF}
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end;
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@ -1,9 +1,8 @@
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{
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This file is part of the Free Pascal run time library.
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Copyright (c) 1999-2000 by Jonas Maebe,
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member of the Free Pascal development team.
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Copyright (c) 2005 by Thomas Schatzl
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TSigContext
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TSigContext and associated structures
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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@ -17,65 +16,151 @@
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{$packrecords C}
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type
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TPPC_Reg = QWord;
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gpr_reg = cULong;
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fpr_reg = double;
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vvr_reg = array[0..1] of cULong;
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type
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{ from include/asm-ppc64/ptrace.h }
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pptregs = ^tptregs;
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tptregs = record
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gpr: array[0..31] of TPPC_Reg;
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nip: TPPC_Reg;
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msr: TPPC_Reg;
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orig_gpr3: TPPC_Reg; { Used for restarting system calls }
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ctr: TPPC_Reg;
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link: TPPC_Reg;
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xer: TPPC_Reg;
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ccr: TPPC_Reg;
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softe: TPPC_Reg; { soft enabled/disabled }
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trap: TPPC_Reg; { Reason for being here }
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dar: TPPC_Reg; { Fault registers }
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dsisr: TPPC_Reg;
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result: TPPC_Reg; { Result of a system call }
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ppt_regs = ^pt_regs;
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pt_regs = record
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gpr : array[0..31] of gpr_reg;
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nip : gpr_reg;
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msr : gpr_reg;
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orig_gpr3 : gpr_reg; { Used for restarting system calls }
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ctr : gpr_reg;
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link : gpr_reg;
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xer : gpr_reg;
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ccr : gpr_reg;
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softe : gpr_reg; { Soft enabled/disabled }
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trap : gpr_reg; { Reason for being here }
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dar : gpr_reg; { Fault registers }
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dsisr : gpr_reg;
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result : gpr_reg; { Result of a system call }
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end;
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{ index constants for the different register set arrays in TSigContext.
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Comments were directly pasted from the sources.
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}
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const
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PT_R0 = 0;
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PT_R1 = 1;
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PT_R2 = 2;
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PT_R3 = 3;
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PT_R4 = 4;
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PT_R5 = 5;
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PT_R6 = 6;
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PT_R7 = 7;
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PT_R8 = 8;
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PT_R9 = 9;
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PT_R10 = 10;
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PT_R11 = 11;
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PT_R12 = 12;
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PT_R13 = 13;
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PT_R14 = 14;
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PT_R15 = 15;
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PT_R16 = 16;
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PT_R17 = 17;
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PT_R18 = 18;
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PT_R19 = 19;
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PT_R20 = 20;
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PT_R21 = 21;
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PT_R22 = 22;
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PT_R23 = 23;
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PT_R24 = 24;
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PT_R25 = 25;
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PT_R26 = 26;
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PT_R27 = 27;
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PT_R28 = 28;
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PT_R29 = 29;
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PT_R30 = 30;
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PT_R31 = 31;
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PT_NIP = 32;
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PT_MSR = 33;
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PT_CTR = 35;
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PT_LNK = 36;
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PT_XER = 37;
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PT_CCR = 38;
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PT_SOFTE = 39;
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PT_RESULT = 43;
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PT_FPR0 = 48;
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PT_FPR31 = PT_FPR0+31;
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{ Kernel and userspace will both use this PT_FPSCR value. 32-bit apps will have
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visibility to the asm-ppc/ptrace.h header instead of this one. }
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{ each FP reg occupies 1 slot in 64-bit space }
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PT_FPSCR = PT_FPR0+32;
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{ each Vector reg occupies 2 slots in 64-bit }
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PT_VR0 = 82;
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PT_VSCR = (PT_VR0+(32*2))+1;
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PT_VRSAVE = PT_VR0+(33*2);
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{ from include/asm-ppc64/signal.h }
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type
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stack_t = record
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ss_sp: pointer;
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ss_flags: longint;
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ss_size: size_t;
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ss_sp : pointer;
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ss_flags : cInt;
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ss_size : size_t;
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end;
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{ from include/asm-ppc64/sigcontext.h }
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tsigcontext_struct = record
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_unused: array[0..3] of qword;
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signal: longint;
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pad0 : longint;
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handler: qword;
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oldmask: qword;
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pt_regs: pptregs;
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{ from include/asm-ppc64/sigcontext.h and
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include/asm-ppc64/elf.h
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}
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const
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ELF_NGREG = 48; { includes nip, msr, lr, etc. }
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ELF_NFPREG = 33; { includes fpscr }
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ELF_NVRREG = 34; { includes vscr & vrsave in split vectors }
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type
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elf_gregset_t = array[0..ELF_NGREG-1] of gpr_reg;
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elf_fpregset_t = array[0..ELF_NFPREG-1] of fpr_reg;
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elf_vrreg_t = array[0..ELF_NVRREG-1] of vvr_reg;
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TSigContext = record
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_unused : array[0..3] of cULong;
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signal : cInt;
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_pad0 : cInt;
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handler : cULong;
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oldmask : cULong;
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regs : ppt_regs;
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gp_regs : elf_gregset_t;
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fp_regs : elf_fpregset_t;
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{ To maintain compatibility with current implementations the sigcontext is
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extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
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followed by an unstructured (vmx_reserve) field of 69 doublewords. This
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allows the array of vector registers to be quadword aligned independent of
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the alignment of the containing sigcontext or ucontext. It is the
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responsibility of the code setting the sigcontext to set this pointer to
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either NULL (if this processor does not support the VMX feature) or the
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address of the first quadword within the allocated (vmx_reserve) area.
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The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
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an array of 34 quadword entries (elf_vrregset_t). The entries with
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indexes 0-31 contain the corresponding vector registers. The entry with
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index 32 contains the vscr as the last word (offset 12) within the
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quadword. This allows the vscr to be stored as either a quadword (since
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it must be copied via a vector register to/from storage) or as a word.
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The entry with index 33 contains the vrsave as the first word (offset 0)
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within the quadword. }
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v_regs : ^elf_vrreg_t;
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vmx_reserve : array[0..ELF_NVRREG+ELF_NVRREG] of cLong;
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end;
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{ the kernel uses a different sigset_t type for the ucontext structure and the
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sigset_t used for masking signals. To avoid name clash, and still use a dedicated
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type for the fields, use _sigset_t }
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_sigset_t = cULong;
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{ from include/asm-ppc64/ucontext.h }
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pucontext = ^tucontext;
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tucontext = record
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uc_flags : qword;
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uc_flags : cuLong;
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uc_link : pucontext;
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uc_stack : stack_t;
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uc_sigmask : qword;{sigset_t;}
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__unused : array[0..14] of qword;{sigset_t;}
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uc_mcontext : tsigcontext_struct;
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end;
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{ from arch/ppc/kernel/signal.c, the type of the actual parameter passed }
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{ to the sigaction handler }
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t_rt_sigframe = record
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uc: tucontext;
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_unused: array[0..1] of qword;
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tramp: array[0..5] of dword;
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pinfo: psiginfo;
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puc: pointer;
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siginfo: tsiginfo;
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abigap: array[0..287] of byte;
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uc_sigmask : _sigset_t;
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__unused : array[0..14] of _sigset_t; { Allow for uc_sigmask growth }
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uc_mcontext : TSigContext; { last for extensibility }
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end;
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PSigContext = ^TSigContext;
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TSigContext= tsigcontext_struct;
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@ -21,14 +21,14 @@
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{****************************************************************************
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PowerPC specific stuff
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****************************************************************************}
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{
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const
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ppc_fpu_overflow = (1 shl (32-3));
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ppc_fpu_underflow = (1 shl (32-4));
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ppc_fpu_divbyzero = (1 shl (32-5));
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ppc_fpu_inexact = (1 shl (32-6));
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ppc_fpu_invalid_snan = (1 shl (32-7));
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}
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procedure fpc_enable_ppc_fpu_exceptions;
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assembler; nostackframe;
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@ -67,12 +67,12 @@ asm
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stfd f0,temp
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lwz r3,temp.b
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{ clear all exception flags }
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{
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{ TODO
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rlwinm r4,r3,0,16,31
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stw r4,temp.b
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lfd f0,temp
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a_mtfsf f0
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}
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mtfsf f0
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}
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end;
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@ -930,20 +930,16 @@ asm
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mr r3, r1
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end;
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{NOTE: On MACOS, 68000 code might call powerpc code, through the MixedMode manager,
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(even in the OS in system 9). The pointer to the switching stack frame is
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indicated by the first bit set to 1. This is checked below.}
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{$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
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function get_caller_addr(framebp:pointer):pointer;assembler;{$ifdef SYSTEMINLINE}inline;{$endif} nostackframe;
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asm
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cmpldi r3,0
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beq .Lcaller_addr_frame_null
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ld r3,0(r3)
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ld r3, 0(r3)
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cmpldi r3,0
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beq .Lcaller_addr_frame_null
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ld r3,16(r3)
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ld r3, 16(r3)
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.Lcaller_addr_frame_null:
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end;
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@ -953,7 +949,7 @@ function get_caller_frame(framebp:pointer):pointer;assembler;{$ifdef SYSTEMINLIN
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asm
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cmpldi r3,0
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beq .Lcaller_frame_null
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ld r3,0(r3)
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ld r3, 0(r3)
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.Lcaller_frame_null:
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end;
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