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* don't convert the fpu parameters size from tcgsize -> int -> float_tcgsize
if not required, to avoid translating OS_C64 into OS_F64 (fix for x86
test failures after r45205)
git-svn-id: trunk@45221 -
This commit is contained in:
Jonas Maebe
parent
de805fddcd
commit
3f6ad30b69
compiler
@ -473,6 +473,8 @@ interface
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the source }
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procedure removeshuffles(var shuffle : tmmshuffle);
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function is_float_cgsize(size: tcgsize): boolean;{$ifdef USEINLINE}inline;{$endif}
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implementation
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uses
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@ -858,6 +860,12 @@ implementation
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end;
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function is_float_cgsize(size: tcgsize): boolean;{$ifdef USEINLINE}inline;{$endif}
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begin
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result:=size in [OS_F32..OS_F128];
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end;
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procedure Initmms(var p : pmmshuffle;len : ShortInt);
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var
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i : Integer;
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@ -1023,144 +1023,151 @@ implementation
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location: pcgparalocation;
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orgsizeleft,
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sizeleft: tcgint;
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usesize: tcgsize;
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reghasvalue: boolean;
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begin
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location:=cgpara.location;
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tmpref:=r;
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sizeleft:=cgpara.intsize;
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while assigned(location) do
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begin
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paramanager.allocparaloc(list,location);
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case location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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begin
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{ Parameter locations are often allocated in multiples of
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entire registers. If a parameter only occupies a part of
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such a register (e.g. a 16 bit int on a 32 bit
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architecture), the size of this parameter can only be
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determined by looking at the "size" parameter of this
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method -> if the size parameter is <= sizeof(aint), then
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we check that there is only one parameter location and
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then use this "size" to load the value into the parameter
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location }
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if (size<>OS_NO) and
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(tcgsize2size[size]<=sizeof(aint)) then
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begin
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cgpara.check_simple_location;
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a_load_ref_reg(list,size,location^.size,tmpref,location^.register);
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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end
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{ there's a lot more data left, and the current paraloc's
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register is entirely filled with part of that data }
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else if (sizeleft>sizeof(aint)) then
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begin
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a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
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end
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{ we're at the end of the data, and it can be loaded into
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the current location's register with a single regular
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load }
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else if sizeleft in [1,2,4,8] then
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begin
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a_load_ref_reg(list,int_cgsize(sizeleft),location^.size,tmpref,location^.register);
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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end
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{ we're at the end of the data, and we need multiple loads
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to get it in the register because it's an irregular size }
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else
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begin
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{ should be the last part }
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if assigned(location^.next) then
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internalerror(2010052907);
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{ load the value piecewise to get it into the register }
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orgsizeleft:=sizeleft;
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reghasvalue:=false;
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repeat
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paramanager.allocparaloc(list,location);
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case location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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begin
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{ Parameter locations are often allocated in multiples of
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entire registers. If a parameter only occupies a part of
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such a register (e.g. a 16 bit int on a 32 bit
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architecture), the size of this parameter can only be
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determined by looking at the "size" parameter of this
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method -> if the size parameter is <= sizeof(aint), then
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we check that there is only one parameter location and
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then use this "size" to load the value into the parameter
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location }
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if (size<>OS_NO) and
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(tcgsize2size[size]<=sizeof(aint)) then
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begin
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cgpara.check_simple_location;
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a_load_ref_reg(list,size,location^.size,tmpref,location^.register);
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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end
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{ there's a lot more data left, and the current paraloc's
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register is entirely filled with part of that data }
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else if (sizeleft>sizeof(aint)) then
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begin
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a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
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end
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{ we're at the end of the data, and it can be loaded into
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the current location's register with a single regular
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load }
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else if sizeleft in [1,2,4,8] then
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begin
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a_load_ref_reg(list,int_cgsize(sizeleft),location^.size,tmpref,location^.register);
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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end
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{ we're at the end of the data, and we need multiple loads
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to get it in the register because it's an irregular size }
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else
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begin
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{ should be the last part }
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if assigned(location^.next) then
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internalerror(2010052907);
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{ load the value piecewise to get it into the register }
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orgsizeleft:=sizeleft;
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reghasvalue:=false;
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{$ifdef cpu64bitalu}
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if sizeleft>=4 then
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begin
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a_load_ref_reg(list,OS_32,location^.size,tmpref,location^.register);
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dec(sizeleft,4);
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if target_info.endian=endian_big then
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a_op_const_reg(list,OP_SHL,location^.size,sizeleft*8,location^.register);
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inc(tmpref.offset,4);
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reghasvalue:=true;
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end;
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if sizeleft>=4 then
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begin
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a_load_ref_reg(list,OS_32,location^.size,tmpref,location^.register);
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dec(sizeleft,4);
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if target_info.endian=endian_big then
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a_op_const_reg(list,OP_SHL,location^.size,sizeleft*8,location^.register);
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inc(tmpref.offset,4);
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reghasvalue:=true;
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end;
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{$endif cpu64bitalu}
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if sizeleft>=2 then
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begin
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tmpreg:=getintregister(list,location^.size);
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a_load_ref_reg(list,OS_16,location^.size,tmpref,tmpreg);
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dec(sizeleft,2);
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if reghasvalue then
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begin
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if target_info.endian=endian_big then
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a_op_const_reg(list,OP_SHL,location^.size,sizeleft*8,tmpreg)
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else
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a_op_const_reg(list,OP_SHL,location^.size,(orgsizeleft-(sizeleft+2))*8,tmpreg);
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a_op_reg_reg(list,OP_OR,location^.size,tmpreg,location^.register);
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end
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else
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begin
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if target_info.endian=endian_big then
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a_op_const_reg_reg(list,OP_SHL,location^.size,sizeleft*8,tmpreg,location^.register)
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else
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a_load_reg_reg(list,location^.size,location^.size,tmpreg,location^.register);
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end;
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inc(tmpref.offset,2);
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reghasvalue:=true;
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end;
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if sizeleft=1 then
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begin
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tmpreg:=getintregister(list,location^.size);
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a_load_ref_reg(list,OS_8,location^.size,tmpref,tmpreg);
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dec(sizeleft,1);
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if reghasvalue then
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begin
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if target_info.endian=endian_little then
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a_op_const_reg(list,OP_SHL,location^.size,(orgsizeleft-(sizeleft+1))*8,tmpreg);
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a_op_reg_reg(list,OP_OR,location^.size,tmpreg,location^.register)
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end
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else
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a_load_reg_reg(list,location^.size,location^.size,tmpreg,location^.register);
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inc(tmpref.offset);
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end;
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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{ the loop will already adjust the offset and sizeleft }
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dec(tmpref.offset,orgsizeleft);
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sizeleft:=orgsizeleft;
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end;
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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reference_reset_base(ref,location^.reference.index,location^.reference.offset,ctempposinvalid,newalignment(cgpara.alignment,cgpara.intsize-sizeleft),[]);
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a_load_ref_cgparalocref(list,size,sizeleft,tmpref,ref,cgpara,location);
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end;
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LOC_MMREGISTER,LOC_CMMREGISTER:
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begin
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case location^.size of
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OS_F32,
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OS_F64,
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OS_F128:
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a_loadmm_ref_reg(list,location^.size,location^.size,tmpref,location^.register,mms_movescalar);
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OS_M8..OS_M512:
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a_loadmm_ref_reg(list,location^.size,location^.size,tmpref,location^.register,nil);
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else
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internalerror(2010053101);
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if sizeleft>=2 then
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begin
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tmpreg:=getintregister(list,location^.size);
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a_load_ref_reg(list,OS_16,location^.size,tmpref,tmpreg);
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dec(sizeleft,2);
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if reghasvalue then
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begin
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if target_info.endian=endian_big then
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a_op_const_reg(list,OP_SHL,location^.size,sizeleft*8,tmpreg)
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else
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a_op_const_reg(list,OP_SHL,location^.size,(orgsizeleft-(sizeleft+2))*8,tmpreg);
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a_op_reg_reg(list,OP_OR,location^.size,tmpreg,location^.register);
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end
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else
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begin
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if target_info.endian=endian_big then
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a_op_const_reg_reg(list,OP_SHL,location^.size,sizeleft*8,tmpreg,location^.register)
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else
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a_load_reg_reg(list,location^.size,location^.size,tmpreg,location^.register);
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end;
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inc(tmpref.offset,2);
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reghasvalue:=true;
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end;
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if sizeleft=1 then
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begin
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tmpreg:=getintregister(list,location^.size);
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a_load_ref_reg(list,OS_8,location^.size,tmpref,tmpreg);
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dec(sizeleft,1);
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if reghasvalue then
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begin
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if target_info.endian=endian_little then
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a_op_const_reg(list,OP_SHL,location^.size,(orgsizeleft-(sizeleft+1))*8,tmpreg);
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a_op_reg_reg(list,OP_OR,location^.size,tmpreg,location^.register)
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end
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else
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a_load_reg_reg(list,location^.size,location^.size,tmpreg,location^.register);
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inc(tmpref.offset);
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end;
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if location^.shiftval<0 then
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a_op_const_reg(list,OP_SHL,location^.size,-location^.shiftval,location^.register);
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{ the loop will already adjust the offset and sizeleft }
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dec(tmpref.offset,orgsizeleft);
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sizeleft:=orgsizeleft;
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end;
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end;
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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begin
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a_loadfpu_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
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end
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else
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internalerror(2010053111);
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end;
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inc(tmpref.offset,tcgsize2size[location^.size]);
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dec(sizeleft,tcgsize2size[location^.size]);
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location:=location^.next;
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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reference_reset_base(ref,location^.reference.index,location^.reference.offset,ctempposinvalid,newalignment(cgpara.alignment,cgpara.intsize-sizeleft),[]);
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a_load_ref_cgparalocref(list,size,sizeleft,tmpref,ref,cgpara,location);
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end;
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LOC_MMREGISTER,LOC_CMMREGISTER:
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begin
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case location^.size of
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OS_F32,
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OS_F64,
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OS_F128:
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a_loadmm_ref_reg(list,location^.size,location^.size,tmpref,location^.register,mms_movescalar);
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OS_M8..OS_M512:
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a_loadmm_ref_reg(list,location^.size,location^.size,tmpref,location^.register,nil);
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else
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internalerror(2010053101);
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end;
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end;
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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begin
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{ can be not a float size in case of a record passed in fpu registers }
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{ the size comparison is to catch F128 passed in two 64 bit floating point registers }
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if is_float_cgsize(size) and
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(tcgsize2size[location^.size]>=tcgsize2size[size]) then
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usesize:=size
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else
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usesize:=location^.size;
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a_loadfpu_ref_reg(list,usesize,location^.size,tmpref,location^.register);
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end
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else
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internalerror(2010053111);
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end;
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inc(tmpref.offset,tcgsize2size[location^.size]);
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dec(sizeleft,tcgsize2size[location^.size]);
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location:=location^.next;
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until not assigned(location);
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end;
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procedure tcg.a_load_ref_cgparalocref(list: TAsmList; sourcesize: tcgsize; sizeleft: tcgint; const ref, paralocref: treference; const cgpara: tcgpara; const location: PCGParaLocation);
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@ -1884,6 +1891,7 @@ implementation
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var
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srcref,
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href : treference;
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srcsize,
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hsize: tcgsize;
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paraloc: PCGParaLocation;
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sizeleft: tcgint;
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@ -1896,9 +1904,18 @@ implementation
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case paraloc^.loc of
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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begin
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{ force fpu size }
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hsize:=int_float_cgsize(tcgsize2size[paraloc^.size]);
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a_loadfpu_ref_reg(list,hsize,hsize,srcref,paraloc^.register);
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{ destination: can be something different in case of a record passed in fpu registers }
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if is_float_cgsize(paraloc^.size) then
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hsize:=paraloc^.size
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else
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hsize:=int_float_cgsize(tcgsize2size[paraloc^.size]);
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{ source: the size comparison is to catch F128 passed in two 64 bit floating point registers }
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if is_float_cgsize(size) and
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(tcgsize2size[size]<=tcgsize2size[paraloc^.size]) then
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srcsize:=size
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else
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srcsize:=hsize;
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a_loadfpu_ref_reg(list,srcsize,hsize,srcref,paraloc^.register);
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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