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* Xtensa: patch by Christo Crause to handle the sign extension architecture option, resolves #36885

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git-svn-id: trunk@44689 -
This commit is contained in:
florian 2020-04-11 14:58:58 +00:00
parent f2d45a0e9d
commit 4141df7fe6
4 changed files with 26 additions and 5 deletions
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24
compiler/xtensa/cgcpu.pas
View File

@ -179,14 +179,26 @@ implementation
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8)); list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8));
OS_S8: OS_S8:
begin begin
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7)); if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7))
else
begin
list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,24));
list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,24));
end;
if tosize=OS_16 then if tosize=OS_16 then
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16)); list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16));
end; end;
OS_16: OS_16:
list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16)); list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16));
OS_S16: OS_S16:
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15)); if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15))
else
begin
list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,16));
list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,16));
end;
else else
conv_done:=false; conv_done:=false;
end; end;
@ -270,7 +282,13 @@ implementation
list.concat(taicpu.op_reg_ref(op,reg,href)); list.concat(taicpu.op_reg_ref(op,reg,href));
if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7)); if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7))
else
begin
list.concat(taicpu.op_reg_reg_const(A_SLLI,reg,reg,24));
list.concat(taicpu.op_reg_reg_const(A_SRAI,reg,reg,24));
end;
if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
a_load_reg_reg(list,fromsize,tosize,reg,reg); a_load_reg_reg(list,fromsize,tosize,reg,reg);
end; end;

5
compiler/xtensa/cpuinfo.pas
View File

@ -135,7 +135,8 @@ Const
type type
tcpuflags = tcpuflags =
( (
CPUXTENSA_REGWINDOW CPUXTENSA_REGWINDOW,
CPUXTENSA_HAS_SEXT
); );
tfpuflags = tfpuflags =
@ -149,7 +150,7 @@ Const
( (
{ cpu_none } [], { cpu_none } [],
{ cpu_lx106 } [], { cpu_lx106 } [],
{ cpu_lx6 } [CPUXTENSA_REGWINDOW] { cpu_lx6 } [CPUXTENSA_REGWINDOW, CPUXTENSA_HAS_SEXT]
); );
fpu_capabilities : array[tfputype] of set of tfpuflags = fpu_capabilities : array[tfputype] of set of tfpuflags =

1
compiler/xtensa/xtensaatt.inc
View File

@ -48,6 +48,7 @@
'sll', 'sll',
'slli', 'slli',
'sra', 'sra',
'srai',
'srl', 'srl',
'srli', 'srli',
'ssi', 'ssi',

1
compiler/xtensa/xtensaop.inc
View File

@ -48,6 +48,7 @@ A_SEXT,
A_SLL, A_SLL,
A_SLLI, A_SLLI,
A_SRA, A_SRA,
A_SRAI,
A_SRL, A_SRL,
A_SRLI, A_SRLI,
A_SSI, A_SSI,