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+ SPARC: support 8 and 16-bit arithmetic shifts.
git-svn-id: trunk@26330 -
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399129693f
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@ -756,6 +756,20 @@ implementation
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procedure TCgSparc.a_op_reg_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);
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begin
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if (TOpcg2AsmOp[op]=A_NONE) then
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InternalError(2013070305);
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if (op=OP_SAR) then
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begin
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if (size in [OS_S8,OS_S16]) then
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begin
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{ Sign-extend before shifting }
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list.concat(taicpu.op_reg_const_reg(A_SLL,src2,32-(tcgsize2size[size]*8),dst));
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list.concat(taicpu.op_reg_const_reg(A_SRA,dst,32-(tcgsize2size[size]*8),dst));
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src2:=dst;
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end
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else if not (size in [OS_32,OS_S32]) then
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InternalError(2013070306);
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end;
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list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst));
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maybeadjustresult(list,op,size,dst);
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end;
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@ -779,6 +793,18 @@ implementation
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a_load_const_reg(list,size,a,dst);
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exit;
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end;
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OP_SAR:
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begin
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if (size in [OS_S8,OS_S16]) then
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLL,src,32-(tcgsize2size[size]*8),dst));
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inc(a,32-tcgsize2size[size]*8);
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src:=dst;
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end
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else if not (size in [OS_32,OS_S32]) then
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InternalError(2013070303);
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end;
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end;
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if setflags then
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begin
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@ -905,10 +905,10 @@ function RolQWord(Const AValue : QWord;const Dist : Byte): QWord;{$ifdef SYSTEMI
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{$ifdef FPC_HAS_INTERNAL_SAR}
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{$if defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)}
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{$if defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel) or defined(sparc)}
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{$define FPC_HAS_INTERNAL_SAR_BYTE}
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{$define FPC_HAS_INTERNAL_SAR_WORD}
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{$endif defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)}
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{$endif defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel) or defined(sparc)}
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{ currently, all supported CPUs have an internal 32 bit sar implementation }
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{ $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(mips) or defined(mipsel)}
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