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+ SPARC: support 8 and 16-bit arithmetic shifts.

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git-svn-id: trunk@26330 -
This commit is contained in:
sergei 2013-12-30 23:37:21 +00:00
parent 399129693f
commit 4168388235
2 changed files with 28 additions and 2 deletions
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26
compiler/sparc/cgcpu.pas
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@ -756,6 +756,20 @@ implementation
procedure TCgSparc.a_op_reg_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;src1, src2, dst:tregister); procedure TCgSparc.a_op_reg_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);
begin begin
if (TOpcg2AsmOp[op]=A_NONE) then
InternalError(2013070305);
if (op=OP_SAR) then
begin
if (size in [OS_S8,OS_S16]) then
begin
{ Sign-extend before shifting }
list.concat(taicpu.op_reg_const_reg(A_SLL,src2,32-(tcgsize2size[size]*8),dst));
list.concat(taicpu.op_reg_const_reg(A_SRA,dst,32-(tcgsize2size[size]*8),dst));
src2:=dst;
end
else if not (size in [OS_32,OS_S32]) then
InternalError(2013070306);
end;
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst)); list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst));
maybeadjustresult(list,op,size,dst); maybeadjustresult(list,op,size,dst);
end; end;
@ -779,6 +793,18 @@ implementation
a_load_const_reg(list,size,a,dst); a_load_const_reg(list,size,a,dst);
exit; exit;
end; end;
OP_SAR:
begin
if (size in [OS_S8,OS_S16]) then
begin
list.concat(taicpu.op_reg_const_reg(A_SLL,src,32-(tcgsize2size[size]*8),dst));
inc(a,32-tcgsize2size[size]*8);
src:=dst;
end
else if not (size in [OS_32,OS_S32]) then
InternalError(2013070303);
end;
end; end;
if setflags then if setflags then
begin begin

4
rtl/inc/systemh.inc
View File

@ -905,10 +905,10 @@ function RolQWord(Const AValue : QWord;const Dist : Byte): QWord;{$ifdef SYSTEMI
{$ifdef FPC_HAS_INTERNAL_SAR} {$ifdef FPC_HAS_INTERNAL_SAR}
{$if defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)} {$if defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel) or defined(sparc)}
{$define FPC_HAS_INTERNAL_SAR_BYTE} {$define FPC_HAS_INTERNAL_SAR_BYTE}
{$define FPC_HAS_INTERNAL_SAR_WORD} {$define FPC_HAS_INTERNAL_SAR_WORD}
{$endif defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel)} {$endif defined(cpux86_64) or defined(cpui386) or defined(mips) or defined(mipsel) or defined(sparc)}
{ currently, all supported CPUs have an internal 32 bit sar implementation } { currently, all supported CPUs have an internal 32 bit sar implementation }
{ $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(mips) or defined(mipsel)} { $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(mips) or defined(mipsel)}