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https://gitlab.com/freepascal.org/fpc/source.git
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+ implemented 64-bit shl and shr for i8086
git-svn-id: branches/i8086@23882 -
This commit is contained in:
nickysn
parent
fbc41991f9
commit
43dba74a5c
@ -50,7 +50,7 @@ implementation
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uses
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globtype,systems,constexp,
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cutils,verbose,globals,
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symconst,symdef,aasmbase,aasmtai,aasmdata,defutil,
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symconst,symdef,aasmbase,aasmtai,aasmdata,aasmcpu,defutil,
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cgbase,pass_2,
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ncon,
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cpubase,cpuinfo,
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@ -354,7 +354,7 @@ implementation
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{*****************************************************************************
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TI386SHLRSHRNODE
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TI8086SHLRSHRNODE
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*****************************************************************************}
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@ -368,6 +368,7 @@ implementation
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hreg64hi,hreg64lo:Tregister;
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v : TConstExprInt;
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l1,l2,l3:Tasmlabel;
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ai: taicpu;
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begin
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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@ -376,93 +377,93 @@ implementation
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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if right.nodetype=ordconstn then
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v:=Tordconstnode(right).value and 63;
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{ shifting by 0 directly coded: }
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if (right.nodetype=ordconstn) and (v=0) then
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begin
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v:=Tordconstnode(right).value and 63;
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if v>31 then
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{ ultra hyper fast shift by 0 }
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end
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{ shifting by 1 directly coded: }
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else if (right.nodetype=ordconstn) and (v=1) then
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begin
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if nodetype=shln then
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begin
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if nodetype=shln then
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begin
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
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end
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else
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begin
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
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end;
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=hreg64hi;
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emit_const_reg(A_SHL,S_W,1,hreg64lo);
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emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64lo));
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emit_const_reg(A_RCL,S_W,1,hreg64hi);
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emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64hi));
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end
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else
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begin
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if nodetype=shln then
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begin
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emit_const_reg_reg(A_SHLD,S_L,v.svalue and 31,hreg64lo,hreg64hi);
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emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
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end
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else
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begin
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emit_const_reg_reg(A_SHRD,S_L,v.svalue and 31,hreg64hi,hreg64lo);
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emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
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end;
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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emit_const_reg(A_SHR,S_W,1,GetNextReg(hreg64hi));
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emit_const_reg(A_RCR,S_W,1,hreg64hi);
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emit_const_reg(A_RCR,S_W,1,GetNextReg(hreg64lo));
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emit_const_reg(A_RCR,S_W,1,hreg64lo);
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end;
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end
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else
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begin
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{ load right operators in a register }
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_ECX);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u32inttype,right.location,NR_ECX);
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_CX);
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{ left operator is already in a register }
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{ hence are both in a register }
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{ is it in the case ECX ? }
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{ the damned shift instructions work only til a count of 32 }
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{ so we've to do some tricks here }
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current_asmdata.getjumplabel(l1);
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current_asmdata.getjumplabel(l2);
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current_asmdata.getjumplabel(l3);
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emit_const_reg(A_CMP,S_L,64,NR_ECX);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_L,l1);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l1);
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emit_const_reg(A_CMP,S_L,32,NR_ECX);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_L,l2);
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emit_const_reg(A_SUB,S_L,32,NR_ECX);
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if nodetype=shln then
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{ shifting by a constant? }
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if right.nodetype=ordconstn then
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begin
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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emit_reg_reg(A_MOV,S_L,hreg64lo,hreg64hi);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l2);
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emit_reg_reg_reg(A_SHLD,S_L,NR_CL,hreg64lo,hreg64hi);
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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v:=Tordconstnode(right).value and 63;
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hlcg.a_load_const_reg(current_asmdata.CurrAsmList,u16inttype,v,NR_CX);
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end
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else
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begin
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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emit_reg_reg(A_MOV,S_L,hreg64hi,hreg64lo);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l2);
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emit_reg_reg_reg(A_SHRD,S_L,NR_CL,hreg64hi,hreg64lo);
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u16inttype,right.location,NR_CX);
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{ left operator is already in a register }
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{ hence are both in a register }
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{ is it in the case CX ? }
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end;
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current_asmdata.getjumplabel(l1);
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current_asmdata.getjumplabel(l2);
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current_asmdata.getjumplabel(l3);
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{ for consts, we don't need the extra checks for 0 or >= 64, since
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we've already handled them earlier as a special case }
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if right.nodetype<>ordconstn then
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begin
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emit_const_reg(A_CMP,S_L,64,NR_CX);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_L,l1);
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,hreg64lo,hreg64lo);
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,hreg64hi,hreg64hi);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l1);
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emit_reg_reg(A_TEST,S_W,NR_CX,NR_CX);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_E,l3);
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end;
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cg.a_label(current_asmdata.CurrAsmList,l2);
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if nodetype=shln then
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begin
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emit_const_reg(A_SHL,S_W,1,hreg64lo);
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emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64lo));
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emit_const_reg(A_RCL,S_W,1,hreg64hi);
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emit_const_reg(A_RCL,S_W,1,GetNextReg(hreg64hi));
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end
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else
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begin
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emit_const_reg(A_SHR,S_W,1,GetNextReg(hreg64hi));
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emit_const_reg(A_RCR,S_W,1,hreg64hi);
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emit_const_reg(A_RCR,S_W,1,GetNextReg(hreg64lo));
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emit_const_reg(A_RCR,S_W,1,hreg64lo);
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end;
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ai:=Taicpu.Op_Sym(A_LOOP,S_W,l2);
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ai.is_jmp := True;
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current_asmdata.CurrAsmList.Concat(ai);
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cg.a_label(current_asmdata.CurrAsmList,l3);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_ECX);
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_CX);
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end;
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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end;
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