diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas index 1b44c48df7..da4df4bb52 100644 --- a/compiler/arm/cgcpu.pas +++ b/compiler/arm/cgcpu.pas @@ -715,9 +715,12 @@ unit cgcpu; )); end else} - list.concat(setoppostfix( - taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) - )); + begin + if cgsetflags or setflags then + a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix( + taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)))); + end; if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then begin ovloc.loc:=LOC_FLAGS; @@ -888,9 +891,12 @@ unit cgcpu; end; end; else - list.concat(setoppostfix( - taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) - )); + begin + if cgsetflags or setflags then + a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix( + taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)))); + end; end; maybeadjustresult(list,op,size,dst); end; @@ -2013,9 +2019,11 @@ unit cgcpu; dstref.offset:=size; r:=getintregister(list,size2opsize[size]); a_load_ref_reg(list,size2opsize[size],size2opsize[size],srcref,r); + a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,countreg,countreg,1),PF_S)); a_load_reg_ref(list,size2opsize[size],size2opsize[size],r,dstref); a_jmp_flags(list,F_NE,l); + a_reg_dealloc(list,NR_DEFAULTFLAGS); srcref.offset:=1; dstref.offset:=1; case count mod size of @@ -2718,8 +2726,10 @@ unit cgcpu; case op of OP_NEG: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0),PF_S)); list.concat(taicpu.op_reg_reg_const(A_RSC,regdst.reghi,regsrc.reghi,0)); + cg.a_reg_dealloc(list,NR_DEFAULTFLAGS); end; OP_NOT: begin @@ -2791,11 +2801,15 @@ unit cgcpu; OP_ADD: begin if is_shifter_const(lo(value),b) then - list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,lo(value)),PF_S)) + begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,lo(value)),PF_S)) + end else begin tmpreg:=cg.getintregister(list,OS_32); cg.a_load_const_reg(list,OS_32,lo(value),tmpreg); + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S)); end; @@ -2811,11 +2825,15 @@ unit cgcpu; OP_SUB: begin if is_shifter_const(lo(value),b) then - list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,lo(value)),PF_S)) + begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,lo(value)),PF_S)) + end else begin tmpreg:=cg.getintregister(list,OS_32); cg.a_load_const_reg(list,OS_32,lo(value),tmpreg); + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S)); end; @@ -2854,11 +2872,15 @@ unit cgcpu; OP_ADD: begin if is_shifter_const(aint(lo(value)),b) then - list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S)) + begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S)) + end else begin tmpreg:=cg.getintregister(list,OS_32); cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg); + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S)); end; @@ -2874,11 +2896,15 @@ unit cgcpu; OP_SUB: begin if is_shifter_const(aint(lo(value)),b) then - list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S)) + begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S)) + end else begin tmpreg:=cg.getintregister(list,OS_32); cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg); + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S)); end; @@ -2911,11 +2937,13 @@ unit cgcpu; case op of OP_ADD: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S)); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi),PF_S)); end; OP_SUB: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S)); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi),PF_S)); end; @@ -2944,13 +2972,17 @@ unit cgcpu; end; OP_ADD: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S)); list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi)); + cg.a_reg_dealloc(list,NR_DEFAULTFLAGS); end; OP_SUB: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S)); list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi)); + cg.a_reg_dealloc(list,NR_DEFAULTFLAGS); end; else internalerror(2003083101); @@ -3271,13 +3303,18 @@ unit cgcpu; begin tmpreg:=getintregister(list,size); a_load_const_reg(list, size, a, tmpreg); - list.concat(setoppostfix(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src,tmpreg),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) - )); + if cgsetflags or setflags then + a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix( + taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src,tmpreg),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)))); end else - list.concat(setoppostfix( - taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) - )); + begin + if cgsetflags or setflags then + a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix( + taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)))); + end; if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then begin ovloc.loc:=LOC_FLAGS; @@ -3412,9 +3449,12 @@ unit cgcpu; end; end; else - list.concat(setoppostfix( - taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmopThumb2[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) - )); + begin + if cgsetflags or setflags then + a_reg_alloc(list,NR_DEFAULTFLAGS); + list.concat(setoppostfix( + taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmopThumb2[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)))); + end; end; maybeadjustresult(list,op,size,dst); end; @@ -3810,10 +3850,12 @@ unit cgcpu; case op of OP_NEG: begin + cg.a_reg_alloc(list,NR_DEFAULTFLAGS); list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0),PF_S)); tmpreg:=cg.getintregister(list,OS_32); list.concat(taicpu.op_reg_const(A_MOV,tmpreg,0)); list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,tmpreg,regsrc.reghi)); + cg.a_reg_dealloc(list,NR_DEFAULTFLAGS); end; else inherited a_op64_reg_reg(list, op, size, regsrc, regdst); diff --git a/compiler/arm/narmadd.pas b/compiler/arm/narmadd.pas index 10e3db206c..1b2c821d4e 100644 --- a/compiler/arm/narmadd.pas +++ b/compiler/arm/narmadd.pas @@ -345,6 +345,7 @@ interface if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true); dummyreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size); + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ORR,dummyreg,right.location.register64.reglo,right.location.register64.reghi),PF_S)); end else if (nodetype in [equaln,unequaln]) and diff --git a/compiler/arm/narmcnv.pas b/compiler/arm/narmcnv.pas index 2d32f6e087..bbe36328f2 100644 --- a/compiler/arm/narmcnv.pas +++ b/compiler/arm/narmcnv.pas @@ -189,6 +189,7 @@ implementation begin hregister:=location.register; location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size); + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MVF,location.register,hregister),PF_S)); end; end; diff --git a/compiler/arm/narminl.pas b/compiler/arm/narminl.pas index 76ad10526e..615e4b05e2 100644 --- a/compiler/arm/narminl.pas +++ b/compiler/arm/narminl.pas @@ -351,8 +351,10 @@ implementation hregister:=cg.getintregister(current_asmdata.CurrAsmList,opsize); location:=left.location; location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize); + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MOV,location.register,left.location.register), PF_S)); current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg_const(A_RSB,location.register,location.register, 0), C_MI)); + cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); end; begin diff --git a/compiler/arm/narmmat.pas b/compiler/arm/narmmat.pas index 3a8b195c1d..2c654b91ec 100644 --- a/compiler/arm/narmmat.pas +++ b/compiler/arm/narmmat.pas @@ -121,6 +121,9 @@ implementation else if (tordconstnode(right).value = int64(-1)) then begin // note: only in the signed case possible..., may overflow + if cs_check_overflow in current_settings.localswitches then + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); + current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MVN, resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S)))); end @@ -408,6 +411,9 @@ implementation begin shifterop_reset(so); shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT); + + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); + {Do we shift more than 32 bits?} emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S)); @@ -424,6 +430,8 @@ implementation so.rs:=shiftval2; emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL)); + cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); + {Final adjustments} if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL; so.rs:=shiftval; @@ -455,16 +463,20 @@ implementation if nodetype=shln then begin {Shift left by one by 2 simple 32bit additions} + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S)); emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi)); + cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); end else begin {Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry} shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1; + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S)); so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount} emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so)); + cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); end {A 32bit shift just replaces a register and clears the other} else if v = 32 then diff --git a/compiler/arm/narmset.pas b/compiler/arm/narmset.pas index 136c6f47e2..a2930905ff 100644 --- a/compiler/arm/narmset.pas +++ b/compiler/arm/narmset.pas @@ -91,8 +91,9 @@ implementation if left.location.loc=LOC_CONSTANT then begin hlcg.location_force_reg(current_asmdata.CurrAsmList, right.location, - right.resultdef, right.resultdef, true); + right.resultdef, right.resultdef, true); + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_TST,right.location.register,1 shl (left.location.value-setbase))); end else @@ -110,6 +111,7 @@ implementation shifterop_reset(so); so.rs:=left.location.register; so.shiftmode:=SM_LSL; + cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS); current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_shifterop(A_TST,right.location.register,hregister,so)); end; end;