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* Change first parameter type of function is_continuous_maks to aword type.
Add typecasts where needed to allow for successful compilation of arm-linux target with -CriotR options when building the compiler. git-svn-id: trunk@40314 -
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@ -1037,7 +1037,7 @@ unit cgcpu;
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{ Doing two shifts instead of two bics might allow the peephole optimizer to fold the second shift
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into the following instruction}
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else if (op = OP_AND) and
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is_continuous_mask(a, lsb, width) and
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is_continuous_mask(aword(a), lsb, width) and
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((lsb = 0) or ((lsb + width) = 32)) then
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begin
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shifterop_reset(so);
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@ -4633,7 +4633,7 @@ unit cgcpu;
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list.concat(taicpu.op_reg_reg(A_UXTH,dst,src))
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else if (op = OP_AND) and is_thumb32_imm(not(dword(a))) then
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list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
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else if (op = OP_AND) and is_continuous_mask(not(a), shift, width) then
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else if (op = OP_AND) and is_continuous_mask(aword(not(a)), shift, width) then
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begin
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a_load_reg_reg(list,size,size,src,dst);
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list.concat(taicpu.op_reg_const_const(A_BFC,dst,shift,width))
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@ -377,7 +377,7 @@ unit cpubase;
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doesn't handle ROR_C detection }
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function is_thumb32_imm(d : aint) : boolean;
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function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword):boolean;
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function is_continuous_mask(d : aint;var lsb, width: byte) : boolean;
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function is_continuous_mask(d : aword;var lsb, width: byte) : boolean;
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function dwarf_reg(r:tregister):shortint;
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function dwarf_reg_no_error(r:tregister):shortint;
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@ -610,7 +610,7 @@ unit cpubase;
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end;
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end;
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function is_continuous_mask(d : aint;var lsb, width: byte) : boolean;
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function is_continuous_mask(d : aword;var lsb, width: byte) : boolean;
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var
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msb : byte;
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begin
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@ -619,7 +619,7 @@ unit cpubase;
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width:=msb-lsb+1;
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result:=(lsb<>255) and (msb<>255) and ((((1 shl (msb-lsb+1))-1) shl lsb) = d);
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result:=(lsb<>255) and (msb<>255) and (aword(((1 shl (msb-lsb+1))-1) shl lsb) = d);
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end;
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