mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-09 08:30:54 +02:00
* extracted gen_load_cgpara_loc()
* unified previously introduced helpers into a single gen_load_loc_cgpara()
with the same interface as gen_load_cgpara_loc()
git-svn-id: trunk@15327 -
This commit is contained in:
Jonas Maebe
parent
73df2c730d
commit
46ff0c4fc4
@ -128,15 +128,8 @@ implementation
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if left.location.loc in [LOC_FLAGS,LOC_JUMP,LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF] then
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),false);
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{ Handle Floating point types differently
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This doesn't depend on emulator settings, emulator settings should
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be handled by cpupara }
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if left.resultdef.typ=floatdef then
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gen_loadfpu_loc_cgpara(current_asmdata.CurrAsmList,left.location,tempcgpara,left.resultdef.size)
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else
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gen_load_locnonfpu_cgpara(current_asmdata.CurrAsmList,left.location,tempcgpara,is_64bit(left.resultdef))
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{ load the parameter's tlocation into its cgpara }
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gen_load_loc_cgpara(current_asmdata.CurrAsmList,left.resultdef,left.location,tempcgpara)
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end;
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@ -66,10 +66,15 @@ interface
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procedure location_force_mmregscalar(list:TAsmList;var l: tlocation;maybeconst:boolean);
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procedure location_force_mmreg(list:TAsmList;var l: tlocation;maybeconst:boolean);
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{ load a location of a floatdef into a cgpara }
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procedure gen_loadfpu_loc_cgpara(list:TAsmList;const l: tlocation;const cgpara: tcgpara;locintsize: longint);
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{ load a location of a non-floatdef into a cgpara }
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procedure gen_load_locnonfpu_cgpara(list:TAsmList;const l: tlocation;const cgpara: tcgpara; is64bitint: boolean);
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{ load a tlocation into a cgpara }
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procedure gen_load_loc_cgpara(list: TAsmList; vardef: tdef; const l: tlocation; const cgpara: tcgpara);
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{ loads a cgpara into a tlocation; assumes that loc.loc is already
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initialised }
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procedure gen_load_cgpara_loc(list: TAsmList; vardef: tdef; const para: TCGPara; var destloc: tlocation);
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{ allocate registers for a tlocation; assumes that loc.loc is already
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set to LOC_CREGISTER/LOC_CFPUREGISTER/... }
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procedure gen_alloc_regloc(list:TAsmList;var loc: tlocation);
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procedure register_maybe_adjust_setbase(list: TAsmList; var l: tlocation; setbase: aint);
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@ -923,12 +928,22 @@ implementation
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end;
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procedure gen_load_locnonfpu_cgpara(list: TAsmList; const l: tlocation;const cgpara: tcgpara; is64bitint: boolean);
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procedure gen_load_loc_cgpara(list: TAsmList; vardef: tdef; const l: tlocation; const cgpara: tcgpara);
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{$ifndef cpu64bitalu}
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var
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tmploc: tlocation;
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{$endif not cpu64bitalu}
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begin
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{ Handle Floating point types differently
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This doesn't depend on emulator settings, emulator settings should
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be handled by cpupara }
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if vardef.typ=floatdef then
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begin
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gen_loadfpu_loc_cgpara(list,l,cgpara,vardef.size);
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exit;
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end;
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case l.loc of
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LOC_CONSTANT,
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LOC_REGISTER,
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@ -938,7 +953,7 @@ implementation
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begin
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{$ifndef cpu64bitalu}
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{ use cg64 only for int64, not for 8 byte records }
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if is64bitint then
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if is_64bit(vardef) then
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cg64.a_load64_loc_cgpara(list,l,cgpara)
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else
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{$endif not cpu64bitalu}
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@ -1794,31 +1809,37 @@ implementation
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end;
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procedure gen_alloc_regvar(list:TAsmList;sym: tabstractnormalvarsym);
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procedure gen_alloc_regloc(list:TAsmList;var loc: tlocation);
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begin
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case sym.initialloc.loc of
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case loc.loc of
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LOC_CREGISTER:
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begin
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{$ifndef cpu64bitalu}
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if sym.initialloc.size in [OS_64,OS_S64] then
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if loc.size in [OS_64,OS_S64] then
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begin
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sym.initialloc.register64.reglo:=cg.getintregister(list,OS_32);
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sym.initialloc.register64.reghi:=cg.getintregister(list,OS_32);
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loc.register64.reglo:=cg.getintregister(list,OS_32);
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loc.register64.reghi:=cg.getintregister(list,OS_32);
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end
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else
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{$endif cpu64bitalu}
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sym.initialloc.register:=cg.getintregister(list,sym.initialloc.size);
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loc.register:=cg.getintregister(list,loc.size);
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end;
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LOC_CFPUREGISTER:
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begin
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sym.initialloc.register:=cg.getfpuregister(list,sym.initialloc.size);
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loc.register:=cg.getfpuregister(list,loc.size);
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end;
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LOC_CMMREGISTER:
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begin
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sym.initialloc.register:=cg.getmmregister(list,sym.initialloc.size);
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loc.register:=cg.getmmregister(list,loc.size);
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end;
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end;
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end;
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procedure gen_alloc_regvar(list:TAsmList;sym: tabstractnormalvarsym; allocreg: boolean);
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begin
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if allocreg then
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gen_alloc_regloc(list,sym.initialloc);
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if (pi_has_goto in current_procinfo.flags) then
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begin
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{ Allocate register already, to prevent first allocation to be
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@ -1837,6 +1858,202 @@ implementation
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end;
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procedure gen_load_cgpara_loc(list: TAsmList; vardef: tdef; const para: TCGPara; var destloc: tlocation);
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procedure unget_para(const paraloc:TCGParaLocation);
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begin
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case paraloc.loc of
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LOC_REGISTER :
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begin
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if getsupreg(paraloc.register)<first_int_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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LOC_MMREGISTER :
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begin
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if getsupreg(paraloc.register)<first_mm_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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LOC_FPUREGISTER :
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begin
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if getsupreg(paraloc.register)<first_fpu_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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end;
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end;
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var
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paraloc : pcgparalocation;
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href : treference;
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sizeleft : aint;
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{$if defined(sparc) or defined(arm)}
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tempref : treference;
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{$endif sparc}
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{$ifndef cpu64bitalu}
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reg64: tregister64;
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{$endif not cpu64bitalu}
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begin
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paraloc:=para.location;
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{ skip e.g. empty records }
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if not assigned(paraloc) then
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internalerror(200408203);
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if (paraloc^.loc = LOC_VOID) then
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exit;
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case destloc.loc of
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LOC_REFERENCE :
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begin
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{ If the parameter location is reused we don't need to copy
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anything }
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if not paramanager.param_use_paraloc(para) then
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begin
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href:=destloc.reference;
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sizeleft:=para.intsize;
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while assigned(paraloc) do
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begin
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if (paraloc^.size=OS_NO) then
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begin
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{ Can only be a reference that contains the rest
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of the parameter }
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if (paraloc^.loc<>LOC_REFERENCE) or
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assigned(paraloc^.next) then
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internalerror(2005013010);
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cg.a_load_cgparaloc_ref(list,paraloc^,href,sizeleft,destloc.reference.alignment);
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inc(href.offset,sizeleft);
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sizeleft:=0;
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end
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else
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begin
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cg.a_load_cgparaloc_ref(list,paraloc^,href,tcgsize2size[paraloc^.size],destloc.reference.alignment);
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inc(href.offset,TCGSize2Size[paraloc^.size]);
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dec(sizeleft,TCGSize2Size[paraloc^.size]);
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end;
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unget_para(paraloc^);
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paraloc:=paraloc^.next;
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end;
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end;
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end;
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LOC_CREGISTER :
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begin
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{$ifndef cpu64bitalu}
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if (para.size in [OS_64,OS_S64]) and
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is_64bit(vardef) then
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begin
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case paraloc^.loc of
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LOC_REGISTER:
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begin
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if not assigned(paraloc^.next) then
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internalerror(200410104);
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc);
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{ reg->reg, alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^,destloc.register64.reghi,4);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^.next^,destloc.register64.reglo,4);
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc);
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^,destloc.register64.reglo,4);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^.next^,destloc.register64.reghi,4);
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end;
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end;
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LOC_REFERENCE:
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begin
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gen_alloc_regloc(list,destloc);
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reference_reset_base(href,paraloc^.reference.index,paraloc^.reference.offset,para.alignment);
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cg64.a_load64_ref_reg(list,href,destloc.register64);
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unget_para(paraloc^);
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end;
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else
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internalerror(2005101501);
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end
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end
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else
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{$endif not cpu64bitalu}
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begin
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if assigned(paraloc^.next) then
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internalerror(200410105);
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc);
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cg.a_load_cgparaloc_anyreg(list,destloc.size,paraloc^,destloc.register,sizeof(aint));
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end;
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end;
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LOC_CFPUREGISTER :
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begin
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{$if defined(sparc) or defined(arm)}
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{ Arm and Sparc passes floats in int registers, when loading to fpu register
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we need a temp }
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sizeleft := TCGSize2Size[destloc.size];
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tg.GetTemp(list,sizeleft,sizeleft,tt_normal,tempref);
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href:=tempref;
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while assigned(paraloc) do
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begin
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unget_para(paraloc^);
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cg.a_load_cgparaloc_ref(list,paraloc^,href,sizeleft,destloc.reference.alignment);
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inc(href.offset,TCGSize2Size[paraloc^.size]);
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dec(sizeleft,TCGSize2Size[paraloc^.size]);
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paraloc:=paraloc^.next;
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end;
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gen_alloc_regloc(list,destloc);
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cg.a_loadfpu_ref_reg(list,destloc.size,destloc.size,tempref,destloc.register);
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tg.UnGetTemp(list,tempref);
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{$else sparc}
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc);
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{ from register to register -> alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,destloc.size,paraloc^,destloc.register,0);
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if assigned(paraloc^.next) then
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internalerror(200410109);
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{$endif sparc}
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end;
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LOC_CMMREGISTER :
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begin
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{$ifndef cpu64bitalu}
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{ ARM vfp floats are passed in integer registers }
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if (para.size=OS_F64) and
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(paraloc^.size in [OS_32,OS_S32]) and
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use_vectorfpu(vardef) then
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begin
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{ we need 2x32bit reg }
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if not assigned(paraloc^.next) or
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assigned(paraloc^.next^.next) then
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internalerror(2009112421);
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unget_para(paraloc^);
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unget_para(paraloc^.next^);
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gen_alloc_regloc(list,destloc);
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if (target_info.endian=endian_big) then
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{ paraloc^ -> high
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paraloc^.next -> low }
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reg64:=joinreg64(paraloc^.next^.register,paraloc^.register)
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else
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reg64:=joinreg64(paraloc^.register,paraloc^.next^.register);
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cg64.a_loadmm_intreg64_reg(list,OS_F64,reg64,destloc.register);
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end
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else
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{$endif not cpu64bitalu}
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begin
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unget_para(paraloc^);
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gen_alloc_regloc(list,destloc);
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{ from register to register -> alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,destloc.size,paraloc^,destloc.register,0);
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{ data could come in two memory locations, for now
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we simply ignore the sanity check (FK)
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if assigned(paraloc^.next) then
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internalerror(200410108);
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}
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end;
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end;
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end;
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end;
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procedure gen_load_para_value(list:TAsmList);
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procedure get_para(const paraloc:TCGParaLocation);
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@ -1861,40 +2078,10 @@ implementation
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end;
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procedure unget_para(const paraloc:TCGParaLocation);
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begin
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case paraloc.loc of
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LOC_REGISTER :
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begin
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if getsupreg(paraloc.register)<first_int_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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LOC_MMREGISTER :
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begin
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if getsupreg(paraloc.register)<first_mm_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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LOC_FPUREGISTER :
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begin
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if getsupreg(paraloc.register)<first_fpu_imreg then
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cg.ungetcpuregister(list,paraloc.register);
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end;
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end;
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end;
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var
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i : longint;
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currpara : tparavarsym;
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paraloc : pcgparalocation;
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href : treference;
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sizeleft : aint;
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{$if defined(sparc) or defined(arm)}
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tempref : treference;
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{$endif sparc}
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{$ifndef cpu64bitalu}
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reg64: tregister64;
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{$endif not cpu64bitalu}
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begin
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if (po_assembler in current_procinfo.procdef.procoptions) then
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exit;
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@ -1916,165 +2103,11 @@ implementation
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for i:=0 to current_procinfo.procdef.paras.count-1 do
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begin
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currpara:=tparavarsym(current_procinfo.procdef.paras[i]);
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paraloc:=currpara.paraloc[calleeside].location;
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{ skip e.g. empty records }
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if not assigned(paraloc) then
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internalerror(200408203);
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if (paraloc^.loc = LOC_VOID) then
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continue;
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case currpara.initialloc.loc of
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LOC_REFERENCE :
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begin
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{ If the parameter location is reused we don't need to copy
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anything }
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if not paramanager.param_use_paraloc(currpara.paraloc[calleeside]) then
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begin
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href:=currpara.initialloc.reference;
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sizeleft:=currpara.paraloc[calleeside].intsize;
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while assigned(paraloc) do
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begin
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if (paraloc^.size=OS_NO) then
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begin
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{ Can only be a reference that contains the rest
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of the parameter }
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if (paraloc^.loc<>LOC_REFERENCE) or
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assigned(paraloc^.next) then
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internalerror(2005013010);
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cg.a_load_cgparaloc_ref(list,paraloc^,href,sizeleft,currpara.initialloc.reference.alignment);
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inc(href.offset,sizeleft);
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sizeleft:=0;
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end
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else
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begin
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cg.a_load_cgparaloc_ref(list,paraloc^,href,tcgsize2size[paraloc^.size],currpara.initialloc.reference.alignment);
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inc(href.offset,TCGSize2Size[paraloc^.size]);
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dec(sizeleft,TCGSize2Size[paraloc^.size]);
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end;
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unget_para(paraloc^);
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paraloc:=paraloc^.next;
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end;
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end;
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end;
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LOC_CREGISTER :
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begin
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{$ifndef cpu64bitalu}
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if (currpara.paraloc[calleeside].size in [OS_64,OS_S64]) and
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is_64bit(currpara.vardef) then
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begin
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case paraloc^.loc of
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LOC_REGISTER:
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begin
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if not assigned(paraloc^.next) then
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internalerror(200410104);
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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unget_para(paraloc^);
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gen_alloc_regvar(list,currpara);
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{ reg->reg, alignment is irrelevant }
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^,currpara.initialloc.register64.reghi,4);
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unget_para(paraloc^.next^);
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cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^.next^,currpara.initialloc.register64.reglo,4);
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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unget_para(paraloc^);
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gen_alloc_regvar(list,currpara);
|
||||
cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^,currpara.initialloc.register64.reglo,4);
|
||||
unget_para(paraloc^.next^);
|
||||
cg.a_load_cgparaloc_anyreg(list,OS_32,paraloc^.next^,currpara.initialloc.register64.reghi,4);
|
||||
end;
|
||||
end;
|
||||
LOC_REFERENCE:
|
||||
begin
|
||||
gen_alloc_regvar(list,currpara);
|
||||
reference_reset_base(href,paraloc^.reference.index,paraloc^.reference.offset,currpara.paraloc[calleeside].alignment);
|
||||
cg64.a_load64_ref_reg(list,href,currpara.initialloc.register64);
|
||||
unget_para(paraloc^);
|
||||
end;
|
||||
else
|
||||
internalerror(2005101501);
|
||||
end
|
||||
end
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
begin
|
||||
if assigned(paraloc^.next) then
|
||||
internalerror(200410105);
|
||||
unget_para(paraloc^);
|
||||
gen_alloc_regvar(list,currpara);
|
||||
cg.a_load_cgparaloc_anyreg(list,currpara.initialloc.size,paraloc^,currpara.initialloc.register,sizeof(aint));
|
||||
end;
|
||||
end;
|
||||
LOC_CFPUREGISTER :
|
||||
begin
|
||||
{$if defined(sparc) or defined(arm)}
|
||||
{ Arm and Sparc passes floats in int registers, when loading to fpu register
|
||||
we need a temp }
|
||||
sizeleft := TCGSize2Size[currpara.initialloc.size];
|
||||
tg.GetTemp(list,sizeleft,sizeleft,tt_normal,tempref);
|
||||
href:=tempref;
|
||||
while assigned(paraloc) do
|
||||
begin
|
||||
unget_para(paraloc^);
|
||||
cg.a_load_cgparaloc_ref(list,paraloc^,href,sizeleft,currpara.initialloc.reference.alignment);
|
||||
inc(href.offset,TCGSize2Size[paraloc^.size]);
|
||||
dec(sizeleft,TCGSize2Size[paraloc^.size]);
|
||||
paraloc:=paraloc^.next;
|
||||
end;
|
||||
gen_alloc_regvar(list,currpara);
|
||||
cg.a_loadfpu_ref_reg(list,currpara.initialloc.size,currpara.initialloc.size,tempref,currpara.initialloc.register);
|
||||
tg.UnGetTemp(list,tempref);
|
||||
{$else sparc}
|
||||
unget_para(paraloc^);
|
||||
gen_alloc_regvar(list,currpara);
|
||||
{ from register to register -> alignment is irrelevant }
|
||||
cg.a_load_cgparaloc_anyreg(list,currpara.initialloc.size,paraloc^,currpara.initialloc.register,0);
|
||||
if assigned(paraloc^.next) then
|
||||
internalerror(200410109);
|
||||
{$endif sparc}
|
||||
end;
|
||||
LOC_CMMREGISTER :
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{ ARM vfp floats are passed in integer registers }
|
||||
if (currpara.paraloc[calleeside].size=OS_F64) and
|
||||
(paraloc^.size in [OS_32,OS_S32]) and
|
||||
use_vectorfpu(currpara.vardef) then
|
||||
begin
|
||||
{ we need 2x32bit reg }
|
||||
if not assigned(paraloc^.next) or
|
||||
assigned(paraloc^.next^.next) then
|
||||
internalerror(2009112421);
|
||||
unget_para(paraloc^);
|
||||
unget_para(paraloc^.next^);
|
||||
gen_alloc_regvar(list,currpara);
|
||||
if (target_info.endian=endian_big) then
|
||||
{ paraloc^ -> high
|
||||
paraloc^.next -> low }
|
||||
reg64:=joinreg64(paraloc^.next^.register,paraloc^.register)
|
||||
else
|
||||
reg64:=joinreg64(paraloc^.register,paraloc^.next^.register);
|
||||
cg64.a_loadmm_intreg64_reg(list,OS_F64,reg64,currpara.initialloc.register);
|
||||
end
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
begin
|
||||
unget_para(paraloc^);
|
||||
gen_alloc_regvar(list,currpara);
|
||||
{ from register to register -> alignment is irrelevant }
|
||||
cg.a_load_cgparaloc_anyreg(list,currpara.initialloc.size,paraloc^,currpara.initialloc.register,0);
|
||||
{ data could come in two memory locations, for now
|
||||
we simply ignore the sanity check (FK)
|
||||
if assigned(paraloc^.next) then
|
||||
internalerror(200410108);
|
||||
}
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
gen_load_cgpara_loc(list,currpara.vardef,currpara.paraloc[calleeside],currpara.initialloc);
|
||||
{ gen_load_cgpara_loc() already allocated the initialloc
|
||||
-> don't allocate again }
|
||||
if currpara.initialloc.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMREGISTER] then
|
||||
gen_alloc_regvar(list,currpara,false);
|
||||
end;
|
||||
|
||||
{ generate copies of call by value parameters, must be done before
|
||||
@ -2548,7 +2581,7 @@ implementation
|
||||
begin
|
||||
vs.initialloc.loc:=tvarregable2tcgloc[vs.varregable];
|
||||
vs.initialloc.size:=def_cgsize(vs.vardef);
|
||||
gen_alloc_regvar(list,vs);
|
||||
gen_alloc_regvar(list,vs,true);
|
||||
setlocalloc(vs);
|
||||
end;
|
||||
end;
|
||||
@ -2607,7 +2640,7 @@ implementation
|
||||
else if vs.is_regvar(false) then
|
||||
begin
|
||||
vs.initialloc.loc:=tvarregable2tcgloc[vs.varregable];
|
||||
gen_alloc_regvar(list,vs);
|
||||
gen_alloc_regvar(list,vs,true);
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
Loading…
Reference in New Issue
Block a user