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+ Xtensa: make use of slli and srli

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git-svn-id: trunk@44357 -
This commit is contained in:
florian 2020-03-24 19:42:37 +00:00
parent 222cad35a9
commit 470cc8eb1c
3 changed files with 8 additions and 0 deletions
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4
compiler/xtensa/cgcpu.pas
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@ -469,6 +469,10 @@ implementation
a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst) a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
else if (op=OP_ADD) and (a>=-128) and (a<=127) then else if (op=OP_ADD) and (a>=-128) and (a<=127) then
list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,a)) list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,a))
else if (op=OP_SHL) and (a>=1) and (a<=31) then
list.concat(taicpu.op_reg_reg_const(A_SLLI,dst,src,a))
else if (op=OP_SHR) and (a>=0) and (a<=15) then
list.concat(taicpu.op_reg_reg_const(A_SRLI,dst,src,a))
else else
begin begin
tmpreg:=getintregister(list,size); tmpreg:=getintregister(list,size);

2
compiler/xtensa/xtensaatt.inc
View File

@ -36,8 +36,10 @@
's32i', 's32i',
'sext', 'sext',
'sll', 'sll',
'slli',
'sra', 'sra',
'srl', 'srl',
'srli',
'ssi', 'ssi',
'ssl', 'ssl',
'ssr', 'ssr',

2
compiler/xtensa/xtensaop.inc
View File

@ -36,8 +36,10 @@ A_S16I,
A_S32I, A_S32I,
A_SEXT, A_SEXT,
A_SLL, A_SLL,
A_SLLI,
A_SRA, A_SRA,
A_SRL, A_SRL,
A_SRLI,
A_SSI, A_SSI,
A_SSL, A_SSL,
A_SSR, A_SSR,