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https://gitlab.com/freepascal.org/fpc/source.git
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* factored out TX86AsmOptimizer.OptPass1SHLSAL
git-svn-id: trunk@38498 -
This commit is contained in:
florian
parent
24bf28e126
commit
47927f053a
@ -150,25 +150,6 @@ begin
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end;
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end;
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function InstrReadsFlags(p: tai): boolean;
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var
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l: longint;
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begin
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InstrReadsFlags := true;
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case p.typ of
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ait_instruction:
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if InsProp[taicpu(p).opcode].Ch*
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[Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
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Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
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Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc,Ch_All]<>[] then
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exit;
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ait_label:
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exit;
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end;
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InstrReadsFlags := false;
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end;
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procedure TCPUAsmOptimizer.PrePeepHoleOpts;
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procedure TCPUAsmOptimizer.PrePeepHoleOpts;
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var
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var
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p,hp1: tai;
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p,hp1: tai;
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@ -934,116 +915,8 @@ begin
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end;
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end;
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end;
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end;
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A_SHL, A_SAL:
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A_SHL, A_SAL:
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begin
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if OptPass1SHLSAL(p) then
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if (taicpu(p).oper[0]^.typ = Top_Const) and
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Continue;
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(taicpu(p).oper[1]^.typ = Top_Reg) and
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(taicpu(p).opsize = S_L) and
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(taicpu(p).oper[0]^.val <= 3) then
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{Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
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begin
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TmpBool1 := True; {should we check the next instruction?}
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TmpBool2 := False; {have we found an add/sub which could be
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integrated in the lea?}
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
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while TmpBool1 and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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((((taicpu(hp1).opcode = A_ADD) or
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(taicpu(hp1).opcode = A_SUB)) and
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(taicpu(hp1).oper[1]^.typ = Top_Reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
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(((taicpu(hp1).opcode = A_INC) or
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(taicpu(hp1).opcode = A_DEC)) and
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(taicpu(hp1).oper[0]^.typ = Top_Reg) and
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(taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg))) and
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(not GetNextInstruction(hp1,hp2) or
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not instrReadsFlags(hp2)) Do
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begin
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TmpBool1 := False;
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if (taicpu(hp1).oper[0]^.typ = Top_Const) then
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begin
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TmpBool1 := True;
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TmpBool2 := True;
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case taicpu(hp1).opcode of
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A_ADD:
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inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
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A_SUB:
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dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
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end;
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asml.remove(hp1);
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hp1.free;
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end
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else
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if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
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(((taicpu(hp1).opcode = A_ADD) and
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(TmpRef.base = NR_NO)) or
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(taicpu(hp1).opcode = A_INC) or
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(taicpu(hp1).opcode = A_DEC)) then
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begin
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TmpBool1 := True;
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TmpBool2 := True;
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case taicpu(hp1).opcode of
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A_ADD:
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TmpRef.base := taicpu(hp1).oper[0]^.reg;
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A_INC:
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inc(TmpRef.offset);
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A_DEC:
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dec(TmpRef.offset);
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end;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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if TmpBool2 or
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((current_settings.optimizecputype < cpu_Pentium2) and
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(taicpu(p).oper[0]^.val <= 3) and
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not(cs_opt_size in current_settings.optimizerswitches)) then
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begin
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if not(TmpBool2) and
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(taicpu(p).oper[0]^.val = 1) then
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begin
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hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
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taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
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end
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
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taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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end
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else
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if (current_settings.optimizecputype < cpu_Pentium2) and
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(taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(p).oper[1]^.typ = top_reg) then
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if (taicpu(p).oper[0]^.val = 1) then
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{changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
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but faster on a 486, and Tairable in both U and V pipes on the Pentium
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(unlike shl, which is only Tairable in the U pipe)}
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begin
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hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
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taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end
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else if (taicpu(p).opsize = S_L) and
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(taicpu(p).oper[0]^.val<= 3) then
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{changes "shl $2, %reg" to "lea (,%reg,4), %reg"
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"shl $3, %reg" to "lea (,%reg,8), %reg}
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begin
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
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hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end
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end;
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A_SETcc :
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A_SETcc :
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{ changes
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{ changes
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setcc (funcres) setcc reg
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setcc (funcres) setcc reg
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@ -68,6 +68,7 @@ unit aoptx86;
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function OptPass1OP(const p : tai) : boolean;
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function OptPass1OP(const p : tai) : boolean;
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function OptPass1LEA(var p : tai) : boolean;
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function OptPass1LEA(var p : tai) : boolean;
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function OptPass1Sub(var p : tai) : boolean;
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function OptPass1Sub(var p : tai) : boolean;
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function OptPass1SHLSAL(var p : tai) : boolean;
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function OptPass2MOV(var p : tai) : boolean;
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function OptPass2MOV(var p : tai) : boolean;
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function OptPass2Imul(var p : tai) : boolean;
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function OptPass2Imul(var p : tai) : boolean;
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@ -238,6 +239,25 @@ unit aoptx86;
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end;
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end;
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function InstrReadsFlags(p: tai): boolean;
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var
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l: longint;
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begin
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InstrReadsFlags := true;
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case p.typ of
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ait_instruction:
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if InsProp[taicpu(p).opcode].Ch*
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[Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
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Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
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Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc,Ch_All]<>[] then
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exit;
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ait_label:
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exit;
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end;
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InstrReadsFlags := false;
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end;
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function TX86AsmOptimizer.InstructionLoadsFromReg(const reg: TRegister;const hp: tai): boolean;
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function TX86AsmOptimizer.InstructionLoadsFromReg(const reg: TRegister;const hp: tai): boolean;
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begin
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begin
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Result:=RegReadByInstruction(reg,hp);
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Result:=RegReadByInstruction(reg,hp);
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@ -2054,6 +2074,125 @@ unit aoptx86;
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end;
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end;
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function TX86AsmOptimizer.OptPass1SHLSAL(var p : tai) : boolean;
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var
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TmpBool1,TmpBool2 : Boolean;
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tmpref : treference;
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hp1,hp2: tai;
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begin
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Result:=false;
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if MatchOpType(taicpu(p),top_const,top_reg) and
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(taicpu(p).opsize = S_L) and
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(taicpu(p).oper[0]^.val <= 3) then
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{ Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement }
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begin
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{ should we check the next instruction? }
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TmpBool1 := True;
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{ have we found an add/sub which could be
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integrated in the lea? }
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TmpBool2 := False;
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
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while TmpBool1 and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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((((taicpu(hp1).opcode = A_ADD) or
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(taicpu(hp1).opcode = A_SUB)) and
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(taicpu(hp1).oper[1]^.typ = Top_Reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
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(((taicpu(hp1).opcode = A_INC) or
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(taicpu(hp1).opcode = A_DEC)) and
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(taicpu(hp1).oper[0]^.typ = Top_Reg) and
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(taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg))) and
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(not GetNextInstruction(hp1,hp2) or
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not instrReadsFlags(hp2)) Do
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begin
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TmpBool1 := False;
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if (taicpu(hp1).oper[0]^.typ = Top_Const) then
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begin
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TmpBool1 := True;
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TmpBool2 := True;
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case taicpu(hp1).opcode of
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A_ADD:
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inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
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A_SUB:
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dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
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end;
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asml.remove(hp1);
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hp1.free;
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end
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else
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if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
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(((taicpu(hp1).opcode = A_ADD) and
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(TmpRef.base = NR_NO)) or
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(taicpu(hp1).opcode = A_INC) or
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(taicpu(hp1).opcode = A_DEC)) then
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begin
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TmpBool1 := True;
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TmpBool2 := True;
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case taicpu(hp1).opcode of
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A_ADD:
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TmpRef.base := taicpu(hp1).oper[0]^.reg;
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A_INC:
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inc(TmpRef.offset);
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A_DEC:
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dec(TmpRef.offset);
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end;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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if TmpBool2 or
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((current_settings.optimizecputype < cpu_Pentium2) and
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(taicpu(p).oper[0]^.val <= 3) and
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not(cs_opt_size in current_settings.optimizerswitches)) then
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begin
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if not(TmpBool2) and
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(taicpu(p).oper[0]^.val = 1) then
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begin
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hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
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taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
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end
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
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taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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end
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else if (current_settings.optimizecputype < cpu_Pentium2) and
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MatchOpType(taicpu(p),top_const,top_reg) then
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begin
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{ changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
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but faster on a 486, and Tairable in both U and V pipes on the Pentium
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(unlike shl, which is only Tairable in the U pipe) }
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if taicpu(p).oper[0]^.val=1 then
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begin
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hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
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taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end
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{ changes "shl $2, %reg" to "lea (,%reg,4), %reg"
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"shl $3, %reg" to "lea (,%reg,8), %reg }
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else if (taicpu(p).opsize = S_L) and
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(taicpu(p).oper[0]^.val<= 3) then
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begin
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
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hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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end;
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end;
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function TX86AsmOptimizer.OptPass2MOV(var p : tai) : boolean;
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function TX86AsmOptimizer.OptPass2MOV(var p : tai) : boolean;
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var
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var
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TmpUsedRegs : TAllUsedRegs;
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TmpUsedRegs : TAllUsedRegs;
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