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* patch by ab: Optimized default hash asm in generics.hashes, resolves #40035
* generic.hashes now uses the cpu unit to detect crc32 cpu support
(cherry picked from commit e1bbcf7050)
This commit is contained in:
florian
marcoonthegit
parent
5d878ac342
commit
48ffc20502
@ -122,6 +122,10 @@ var
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mORMotHasher: THasher;
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implementation
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{$ifdef CPUINTEL}
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uses
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cpu;
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{$endif CPUINTEL}
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function SimpleChecksumHash(AKey: Pointer; ALength: SizeInt): UInt32;
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var
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@ -1241,210 +1245,80 @@ end;
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{$ifdef CPUINTEL}
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type
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TRegisters = record
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eax,ebx,ecx,edx: cardinal;
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end;
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{$ifdef CPU64}
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procedure GetCPUID(Param: Cardinal; var Registers: TRegisters); nostackframe; assembler;
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function crc32csse42(crc: cardinal; buf: PAnsiChar; len: cardinal): cardinal; nostackframe; assembler;
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asm
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{$ifdef win64}
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mov eax, ecx
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mov r9, rdx
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{$else}
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mov eax, edi
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mov r9, rsi
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{$endif win64}
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mov r10, rbx // preserve rbx
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xor ebx, ebx
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xor ecx, ecx
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xor edx, edx
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cpuid
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mov TRegisters(r9).&eax, eax
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mov TRegisters(r9).&ebx, ebx
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mov TRegisters(r9).&ecx, ecx
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mov TRegisters(r9).&edx, edx
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mov rbx, r10
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end;
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function crc32csse42(crc: cardinal; buf: Pointer; len: cardinal): cardinal; nostackframe; assembler;
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asm // ecx=crc, rdx=buf, r8=len (Linux: edi,rsi,rdx)
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{$ifdef win64}
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mov eax, ecx
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{$else}
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mov eax, edi
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mov r8, rdx
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mov rdx, rsi
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{$endif win64}
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mov eax, crc
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test len, len
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jz @z
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test buf, buf
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jz @z
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not eax
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test rdx, rdx
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jz @0
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test r8, r8
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jz @0
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@7: test dl, 7
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jz @8 // align to 8 bytes boundary
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crc32 eax, byte ptr[rdx]
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inc rdx
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dec r8
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jz @0
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test dl, 7
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jnz @7
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@8: mov rcx, r8
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shr r8, 3
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mov ecx, len
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shr len, 3
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jnz @by8 // we don't care for read alignment
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@0: test cl, 4
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jz @4
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crc32 eax, dword ptr [buf]
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add buf, 4
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@4: test cl, 2
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jz @2
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@1:
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crc32 rax, qword [rdx] // hash 8 bytes per loop
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dec r8
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lea rdx, [rdx + 8]
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jnz @1
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@2: and ecx, 7
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jz @0
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cmp ecx, 4
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jb @4
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crc32 eax, dword ptr[rdx]
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sub ecx, 4
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lea rdx, [rdx + 4]
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jz @0
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@4: crc32 eax, byte ptr[rdx]
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dec ecx
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jz @0
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crc32 eax, byte ptr[rdx + 1]
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dec ecx
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jz @0
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crc32 eax, byte ptr[rdx + 2]
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@0: not eax
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crc32 eax, word ptr [buf]
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add buf, 2
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@2: test cl, 1
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jz @1
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crc32 eax, byte ptr [buf]
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@1: not eax
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@z: ret
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align 16
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@by8: crc32 rax, qword ptr [buf] // hash 8 bytes per loop
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add buf, 8
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sub len, 1
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jnz @by8
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jmp @0
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end;
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{$endif CPU64}
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{$ifdef CPUX86}
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procedure GetCPUID(Param: Cardinal; var Registers: TRegisters);
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{$else}
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function crc32csse42(crc: cardinal; buf: PAnsiChar; len: cardinal): cardinal; nostackframe; assembler;
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asm
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push esi
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push edi
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mov esi, edx
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mov edi, eax
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pushfd
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pop eax
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mov edx, eax
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xor eax, $200000
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push eax
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popfd
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pushfd
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pop eax
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xor eax, edx
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jz @nocpuid
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push ebx
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mov eax, edi
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xor ecx, ecx
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cpuid
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mov TRegisters(esi).&eax, eax
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mov TRegisters(esi).&ebx, ebx
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mov TRegisters(esi).&ecx, ecx
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mov TRegisters(esi).&edx, edx
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pop ebx
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@nocpuid:
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pop edi
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pop esi
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end;
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function crc32csse42(crc: cardinal; buf: Pointer; len: cardinal): cardinal;
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asm // eax=crc, edx=buf, ecx=len
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// eax=crc, edx=buf, ecx=len
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not eax
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test ecx, ecx
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jz @0
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test edx, edx
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jz @0
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@3: test edx, 3
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jz @8 // align to 4 bytes boundary
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crc32 eax, byte ptr[edx]
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jmp @align
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@a: crc32 eax, byte ptr [edx]
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inc edx
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dec ecx
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jz @0
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test edx, 3
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jnz @3
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@8: push ecx
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@align: test dl, 3
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jnz @a
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push ecx
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shr ecx, 3
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jnz @by8
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@rem: pop ecx
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test cl, 4
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jz @4
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crc32 eax, dword ptr [edx]
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add edx, 4
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@4: test cl, 2
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jz @2
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@1:
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crc32 eax, dword ptr[edx]
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crc32 eax, dword ptr[edx + 4]
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dec ecx
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lea edx, [edx + 8]
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jnz @1
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@2: pop ecx
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and ecx, 7
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crc32 eax, word ptr [edx]
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add edx, 2
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@2: test cl, 1
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jz @0
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cmp ecx, 4
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jb @4
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crc32 eax, dword ptr[edx]
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sub ecx, 4
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lea edx, [edx + 4]
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jz @0
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@4:
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crc32 eax, byte ptr[edx]
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dec ecx
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jz @0
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crc32 eax, byte ptr[edx + 1]
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dec ecx
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jz @0
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crc32 eax, byte ptr[edx + 2]
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crc32 eax, byte ptr [edx]
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@0: not eax
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ret
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@by8: crc32 eax, dword ptr [edx]
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crc32 eax, dword ptr [edx + 4]
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add edx, 8
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dec ecx
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jnz @by8
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jmp @rem
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end;
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{$endif CPUX86}
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{$endif}
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type
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/// the potential features, retrieved from an Intel CPU
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// - see https://en.wikipedia.org/wiki/CPUID#EAX.3D1:_Processor_Info_and_Feature_Bits
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TIntelCpuFeature =
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( { in EDX }
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cfFPU, cfVME, cfDE, cfPSE, cfTSC, cfMSR, cfPAE, cfMCE,
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cfCX8, cfAPIC, cf_d10, cfSEP, cfMTRR, cfPGE, cfMCA, cfCMOV,
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cfPAT, cfPSE36, cfPSN, cfCLFSH, cf_d20, cfDS, cfACPI, cfMMX,
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cfFXSR, cfSSE, cfSSE2, cfSS, cfHTT, cfTM, cfIA64, cfPBE,
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{ in ECX }
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cfSSE3, cfCLMUL, cfDS64, cfMON, cfDSCPL, cfVMX, cfSMX, cfEST,
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cfTM2, cfSSSE3, cfCID, cfSDBG, cfFMA, cfCX16, cfXTPR, cfPDCM,
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cf_c16, cfPCID, cfDCA, cfSSE41, cfSSE42, cfX2A, cfMOVBE, cfPOPCNT,
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cfTSC2, cfAESNI, cfXS, cfOSXS, cfAVX, cfF16C, cfRAND, cfHYP,
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{ extended features in EBX, ECX }
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cfFSGS, cf_b01, cfSGX, cfBMI1, cfHLE, cfAVX2, cf_b06, cfSMEP,
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cfBMI2, cfERMS, cfINVPCID, cfRTM, cfPQM, cf_b13, cfMPX, cfPQE,
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cfAVX512F, cfAVX512DQ, cfRDSEED, cfADX, cfSMAP, cfAVX512IFMA, cfPCOMMIT, cfCLFLUSH,
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cfCLWB, cfIPT, cfAVX512PF, cfAVX512ER, cfAVX512CD, cfSHA, cfAVX512BW, cfAVX512VL,
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cfPREFW1, cfAVX512VBMI, cfUMIP, cfPKU, cfOSPKE, cf_c05, cf_c06, cf_c07,
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cf_c08, cf_c09, cf_c10, cf_c11, cf_c12, cf_c13, cfAVX512VPC, cf_c15,
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cf_cc16, cf_c17, cf_c18, cf_c19, cf_c20, cf_c21, cfRDPID, cf_c23,
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cf_c24, cf_c25, cf_c26, cf_c27, cf_c28, cf_c29, cfSGXLC, cf_c31,
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cf_d0, cf_d1, cfAVX512NNI, cfAVX512MAS, cf_d4, cf_d5, cf_d6, cf_d7);
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/// all features, as retrieved from an Intel CPU
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TIntelCpuFeatures = set of TIntelCpuFeature;
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var
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/// the available CPU features, as recognized at program startup
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CpuFeatures: TIntelCpuFeatures;
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procedure TestIntelCpuFeatures;
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var regs: TRegisters;
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begin
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regs.edx := 0;
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regs.ecx := 0;
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GetCPUID(1,regs);
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PIntegerArray(@CpuFeatures)^[0] := regs.edx;
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PIntegerArray(@CpuFeatures)^[1] := regs.ecx;
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GetCPUID(7,regs);
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PIntegerArray(@CpuFeatures)^[2] := regs.ebx;
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PIntegerArray(@CpuFeatures)^[3] := regs.ecx;
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PByte(@PIntegerArray(@CpuFeatures)^[4])^ := regs.edx;
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// assert(sizeof(CpuFeatures)=4*4+1);
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{$ifdef Darwin}
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{$ifdef CPU64}
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// SSE42 asm does not (yet) work on Darwin x64 ...
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Exclude(CpuFeatures, cfSSE42);
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{$endif}
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{$endif}
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end;
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{$endif CPUINTEL}
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var
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@ -1600,8 +1474,7 @@ end;
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begin
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{$ifdef CPUINTEL}
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TestIntelCpuFeatures;
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if cfSSE42 in CpuFeatures then
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if SSE42Support then
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begin
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crc32c := @crc32csse42;
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mORMotHasher := @crc32csse42;
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