mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-20 04:39:28 +02:00
Fix SWI as a pseudo instruction.
Add VFPv2/3 instruction entries for Thumb2. git-svn-id: branches/laksen/armiw@29356 -
This commit is contained in:
Jeppe Johansen
parent
cbd75428c0
commit
49346b3041
@ -1550,6 +1550,10 @@ implementation
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taicpu(curtai).ops:=2;
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end;
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end;
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A_SWI:
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begin
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taicpu(curtai).opcode:=A_SVC;
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end;
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end;
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end;
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end;
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@ -2317,7 +2321,7 @@ implementation
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// stm,ldm
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#$26,#$69,#$8C,
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// vldm/vstm
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#$44
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#$44,#$94
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]) then
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begin
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Matches:=0;
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@ -3583,7 +3587,7 @@ implementation
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end;
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end;
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end;
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#$40: // VMOV
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#$40,#$90: // VMOV
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -3706,7 +3710,7 @@ implementation
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end;
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end;
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end;
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#$41: // VMRS/VMSR
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#$41,#$91: // VMRS/VMSR
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -3750,7 +3754,7 @@ implementation
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bytes:=bytes or (getsupreg(oper[1]^.reg) shl 12);
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end;
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end;
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#$42: // VMUL
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#$42,#$92: // VMUL
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -3800,7 +3804,7 @@ implementation
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bytes:=bytes or (N shl 7);
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bytes:=bytes or (M shl 5);
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end;
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#$43: // VCVT
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#$43,#$93: // VCVT
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -3962,7 +3966,7 @@ implementation
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bytes:=bytes or ((rn and $1E) shr 1);
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end;
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end;
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#$44: // VLDM/VSTM/VPUSH/VPOP
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#$44,#$94: // VLDM/VSTM/VPUSH/VPOP
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -4079,7 +4083,7 @@ implementation
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end;
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end;
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end;
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#$45: // VLDR/VSTR
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#$45,#$95: // VLDR/VSTR
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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@ -5040,7 +5044,7 @@ implementation
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end;
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{ Todo: Decide whether the code above should take care of writing data in an order that makes senes }
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if (insentry^.code[0] in [#$80..#$90]) and (bytelen=4) then
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if (insentry^.code[0] in [#$80..#$95]) and (bytelen=4) then
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bytes:=((bytes shr 16) and $FFFF) or ((bytes and $FFFF) shl 16);
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{ we're finished, write code }
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@ -401,14 +401,21 @@ reg32,reg32,shifterop \xA\x1\xE0 ARM32,ARMv4
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reg32,immshifter \xB\x1\xE0 ARM32,ARMv4
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[VMOVcc]
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vreg,vreg \x90\xEE\xB0\xA\x40 THUMB32,VFPv2
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vreg,vreg \x40\xE\xB0\xA\x40 ARM32,VFPv2
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reg32,vreg \x90\xEE\x10\xA\x10 THUMB32,VFPv2
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vreg,reg32 \x90\xEE\x00\xA\x10 THUMB32,VFPv2
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reg32,vreg \x40\xE\x10\xA\x10 ARM32,VFPv2
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vreg,reg32 \x40\xE\x00\xA\x10 ARM32,VFPv2
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reg32,reg32,vreg,vreg \x90\xEC\x50\xA\x10 THUMB32,VFPv2
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vreg,vreg,reg32,reg32 \x90\xEC\x40\xA\x10 THUMB32,VFPv2
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reg32,reg32,vreg,vreg \x40\xC\x50\xA\x10 ARM32,VFPv2
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vreg,vreg,reg32,reg32 \x40\xC\x40\xA\x10 ARM32,VFPv2
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reg32,reg32,vreg \x90\xEC\x50\xB\x10 THUMB32,VFPv2
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vreg,reg32,reg32 \x90\xEC\x40\xB\x10 THUMB32,VFPv2
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reg32,reg32,vreg \x40\xC\x50\xB\x10 ARM32,VFPv2
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vreg,reg32,reg32 \x40\xC\x40\xB\x10 ARM32,VFPv2
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@ -552,8 +559,7 @@ reg32,reg32,reg32 \x4\x0\x40 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \x6\x0\x40 ARM32,ARMv4
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[SWIcc]
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imm \x2\x0F ARM32,ARMv4
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immshifter \x2\x0F ARM32,ARMv4
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; Old alias for SVC
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[SWPcc]
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reg32,reg32,memam2 \x27\x10\x09 ARM32,ARMv4
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@ -655,23 +661,31 @@ reg32,reg32,reg32,reg32 \x80\xFB\x30\x0\x10 THUMB32,ARMv6T2
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reg32,reg32,reg32,reg32 \x15\x1\x20\xC ARM32,ARMv5TE
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[VLDMcc]
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memam4,reglist \x94\xEC\x10\xA THUMB32,VFPv2
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reg32,reglist \x94\xEC\x10\xA THUMB32,VFPv2
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memam4,reglist \x44\xC\x10\xA ARM32,VFPv2
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reg32,reglist \x44\xC\x10\xA ARM32,VFPv2
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[VSTMcc]
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memam4,reglist \x94\xEC\x00\xA THUMB32,VFPv2
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reg32,reglist \x94\xEC\x00\xA THUMB32,VFPv2
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memam4,reglist \x44\xC\x00\xA ARM32,VFPv2
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reg32,reglist \x44\xC\x00\xA ARM32,VFPv2
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[VPOP]
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reglist \x94\xEC\xBD\xA THUMB32,VFPv2
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reglist \x44\xC\xBD\xA ARM32,VFPv2
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[VPUSH]
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reglist \x94\xED\x2D\xA THUMB32,VFPv2
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reglist \x44\xD\x2D\xA ARM32,VFPv2
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[VLDRcc]
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vreg,memam2 \x95\xED\x10\xA THUMB32,VFPv2
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vreg,memam2 \x45\xD\x10\xA ARM32,VFPv2
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[VSTRcc]
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vreg,memam2 \x95\xED\x0\xA THUMB32,VFPv2
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vreg,memam2 \x45\xD\x0\xA ARM32,VFPv2
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[SMULBBcc]
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@ -1431,52 +1445,71 @@ reglo,memam2 \x68\xB9 THUMB,ARMv6T2
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; VFP
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[VABScc]
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vreg,vreg \x92\xEE\xB0\xA\xC0 THUMB32,VFPv2
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vreg,vreg \x42\xE\xB0\xA\xC0 ARM32,VFPv2
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[VADDcc]
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vreg,vreg,vreg \x92\xEE\x30\xA\x0 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x30\xA\x0 ARM32,VFPv2
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[VCMPcc]
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vreg,vreg \x92\xEE\xB4\xA\x40 THUMB32,VFPv2
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vreg,immshifter \x92\xEE\xB5\xA\x40 THUMB32,VFPv2
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vreg,vreg \x42\xE\xB4\xA\x40 ARM32,VFPv2
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vreg,immshifter \x42\xE\xB5\xA\x40 ARM32,VFPv2
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[VCMPEcc]
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vreg,vreg \x92\xEE\xB4\xA\xC0 THUMB32,VFPv2
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vreg,immshifter \x92\xEE\xB5\xA\xC0 THUMB32,VFPv2
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vreg,vreg \x42\xE\xB4\xA\xC0 ARM32,VFPv2
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vreg,immshifter \x42\xE\xB5\xA\xC0 ARM32,VFPv2
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[VCVTcc]
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vreg,vreg \x93\xEE\xB8\xA\xC0 THUMB32,VFPv2
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vreg,vreg,immshifter \x93\xEE\xBA\xA\x40 THUMB32,VFPv3
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vreg,vreg \x43\xE\xB8\xA\xC0 ARM32,VFPv2
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vreg,vreg,immshifter \x43\xE\xBA\xA\x40 ARM32,VFPv3
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[VCVTRcc]
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vreg,vreg \x93\xEE\xB8\xA\x40 THUMB32,VFPv2
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vreg,vreg \x43\xE\xB8\xA\x40 ARM32,VFPv2
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[VDIVcc]
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vreg,vreg,vreg \x92\xEE\x80\xA\x0 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x80\xA\x0 ARM32,VFPv2
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[VMRScc]
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reg32,regf \x91\xEE\xF0\xA\x10 THUMB32,VFPv2
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regf,regf \x91\xEE\xF0\xA\x10 THUMB32,VFPv2
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reg32,regf \x41\xE\xF0\xA\x10 ARM32,VFPv2
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regf,regf \x41\xE\xF0\xA\x10 ARM32,VFPv2
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[VMSRcc]
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regf,reg32 \x91\xEE\xE0\xA\x10 THUMB32,VFPv2
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regf,reg32 \x41\xE\xE0\xA\x10 ARM32,VFPv2
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[VMLAcc]
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vreg,vreg,vreg \x92\xEE\x0\xA\x00 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x0\xA\x00 ARM32,VFPv2
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[VMLScc]
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vreg,vreg,vreg \x92\xEE\x0\xA\x40 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x0\xA\x40 ARM32,VFPv2
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[VMULcc]
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vreg,vreg,vreg \x92\xEE\x20\xA\x0 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x20\xA\x0 ARM32,VFPv2
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[VNMLAcc]
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vreg,vreg,vreg \x92\xEE\x10\xA\x40 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x10\xA\x40 ARM32,VFPv2
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[VNMLScc]
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vreg,vreg,vreg \x92\xEE\x10\xA\x00 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x10\xA\x00 ARM32,VFPv2
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[VNMULcc]
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vreg,vreg,vreg \x92\xEE\x20\xA\x40 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x20\xA\x40 ARM32,VFPv2
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[VFMA]
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@ -1485,38 +1518,42 @@ vreg,vreg,vreg \x42\xE\x20\xA\x40 ARM32,VFPv2
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[VFNMS]
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[VNEGcc]
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vreg,vreg \x92\xEE\xB1\xA\x40 THUMB32,VFPv2
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vreg,vreg \x42\xE\xB1\xA\x40 ARM32,VFPv2
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[VSQRT]
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vreg,vreg \x92\xEE\xB1\xA\xC0 THUMB32,VFPv2
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vreg,vreg \x42\xE\xB1\xA\xC0 ARM32,VFPv2
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[VSUB]
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vreg,vreg,vreg \x92\xEE\x30\xA\x40 THUMB32,VFPv2
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vreg,vreg,vreg \x42\xE\x30\xA\x40 ARM32,VFPv2
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[DMB]
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[DMBcc]
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immshifter \x80\xF3\xBF\x8F\x50 THUMB32,ARMv7
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immshifter \x2E\xF5\x7F\xF0\x50 ARM32,ARMv7
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[ISB]
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[ISBcc]
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immshifter \x80\xF3\xBF\x8F\x60 THUMB32,ARMv7
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immshifter \x2E\xF5\x7F\xF0\x60 ARM32,ARMv7
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[DSB]
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[DSBcc]
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immshifter \x80\xF3\xBF\x8F\x40 THUMB32,ARMv7
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immshifter \x2E\xF5\x7F\xF0\x40 ARM32,ARMv7
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[SMC]
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[SMCcc]
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immshifter \x2E\x01\x60\x00\x70 ARM32,ARMv7
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imm32 \x2E\x01\x60\x00\x70 ARM32,ARMv7
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; Thumb armv6-m (gcc)
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[NEG]
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[NEGcc]
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[SVC]
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[SVCcc]
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immshifter \x61\xDF\x0 THUMB,ARMv4T
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imm32 \x61\xDF\x0 THUMB,ARMv4T
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imm32 \x2\x0F ARM32,ARMv4
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immshifter \x2\x0F ARM32,ARMv4
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imm32 \x2\x0F ARM32,ARMv4
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[BXJcc]
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reg32 \x80\xF3\xC0\x8F\x0 THUMB32,ARMv6T2
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@ -1,2 +1,2 @@
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{ don't edit, this file is generated from armins.dat }
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710;
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746;
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@ -1295,6 +1295,13 @@
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code : #11#1#224;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_VMOV;
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ops : 2;
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optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
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code : #144#238#176#10#64;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 2;
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@ -1302,6 +1309,20 @@
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code : #64#14#176#10#64;
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flags : if_arm32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 2;
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optypes : (ot_reg32,ot_vreg,ot_none,ot_none,ot_none,ot_none);
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code : #144#238#16#10#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 2;
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optypes : (ot_vreg,ot_reg32,ot_none,ot_none,ot_none,ot_none);
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code : #144#238#0#10#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 2;
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@ -1316,6 +1337,20 @@
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code : #64#14#0#10#16;
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flags : if_arm32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_vreg,ot_vreg,ot_none,ot_none);
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code : #144#236#80#10#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 4;
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optypes : (ot_vreg,ot_vreg,ot_reg32,ot_reg32,ot_none,ot_none);
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code : #144#236#64#10#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 4;
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@ -1330,6 +1365,20 @@
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code : #64#12#64#10#16;
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flags : if_arm32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_vreg,ot_none,ot_none,ot_none);
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code : #144#236#80#11#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 3;
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optypes : (ot_vreg,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
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code : #144#236#64#11#16;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VMOV;
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ops : 3;
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@ -1995,20 +2044,6 @@
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code : #6#0#64;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_SWI;
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ops : 1;
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optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #2#15;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_SWI;
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ops : 1;
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optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #2#15;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_SWP;
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ops : 3;
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@ -2338,6 +2373,20 @@
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code : #21#1#32#12;
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flags : if_arm32 or if_armv5te
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),
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(
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opcode : A_VLDM;
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ops : 2;
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optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
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code : #148#236#16#10;
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flags : if_thumb32 or if_vfpv2
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),
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(
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opcode : A_VLDM;
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ops : 2;
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optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
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code : #148#236#16#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VLDM;
|
||||
ops : 2;
|
||||
@ -2352,6 +2401,20 @@
|
||||
code : #68#12#16#10;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSTM;
|
||||
ops : 2;
|
||||
optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #148#236#0#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSTM;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #148#236#0#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSTM;
|
||||
ops : 2;
|
||||
@ -2366,6 +2429,13 @@
|
||||
code : #68#12#0#10;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VPOP;
|
||||
ops : 1;
|
||||
optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #148#236#189#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VPOP;
|
||||
ops : 1;
|
||||
@ -2373,6 +2443,13 @@
|
||||
code : #68#12#189#10;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VPUSH;
|
||||
ops : 1;
|
||||
optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #148#237#45#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VPUSH;
|
||||
ops : 1;
|
||||
@ -2380,6 +2457,13 @@
|
||||
code : #68#13#45#10;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VLDR;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #149#237#16#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VLDR;
|
||||
ops : 2;
|
||||
@ -2387,6 +2471,13 @@
|
||||
code : #69#13#16#10;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSTR;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #149#237#0#10;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSTR;
|
||||
ops : 2;
|
||||
@ -4711,6 +4802,13 @@
|
||||
code : #104#185;
|
||||
flags : if_thumb or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_VABS;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#176#10#192;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VABS;
|
||||
ops : 2;
|
||||
@ -4718,6 +4816,13 @@
|
||||
code : #66#14#176#10#192;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VADD;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#48#10#0;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VADD;
|
||||
ops : 3;
|
||||
@ -4725,6 +4830,20 @@
|
||||
code : #66#14#48#10#0;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMP;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#180#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMP;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#181#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMP;
|
||||
ops : 2;
|
||||
@ -4739,6 +4858,20 @@
|
||||
code : #66#14#181#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMPE;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#180#10#192;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMPE;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#181#10#192;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCMPE;
|
||||
ops : 2;
|
||||
@ -4753,6 +4886,20 @@
|
||||
code : #66#14#181#10#192;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCVT;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #147#238#184#10#192;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCVT;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none);
|
||||
code : #147#238#186#10#64;
|
||||
flags : if_thumb32 or if_vfpv3
|
||||
),
|
||||
(
|
||||
opcode : A_VCVT;
|
||||
ops : 2;
|
||||
@ -4767,6 +4914,13 @@
|
||||
code : #67#14#186#10#64;
|
||||
flags : if_arm32 or if_vfpv3
|
||||
),
|
||||
(
|
||||
opcode : A_VCVTR;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #147#238#184#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VCVTR;
|
||||
ops : 2;
|
||||
@ -4774,6 +4928,13 @@
|
||||
code : #67#14#184#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VDIV;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#128#10#0;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VDIV;
|
||||
ops : 3;
|
||||
@ -4781,6 +4942,20 @@
|
||||
code : #66#14#128#10#0;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMRS;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_regf,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #145#238#240#10#16;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMRS;
|
||||
ops : 2;
|
||||
optypes : (ot_regf,ot_regf,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #145#238#240#10#16;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMRS;
|
||||
ops : 2;
|
||||
@ -4795,6 +4970,13 @@
|
||||
code : #65#14#240#10#16;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMSR;
|
||||
ops : 2;
|
||||
optypes : (ot_regf,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #145#238#224#10#16;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMSR;
|
||||
ops : 2;
|
||||
@ -4802,6 +4984,13 @@
|
||||
code : #65#14#224#10#16;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMLA;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#0#10#0;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMLA;
|
||||
ops : 3;
|
||||
@ -4809,6 +4998,13 @@
|
||||
code : #66#14#0#10#0;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMLS;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#0#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMLS;
|
||||
ops : 3;
|
||||
@ -4816,6 +5012,13 @@
|
||||
code : #66#14#0#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMUL;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#32#10#0;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VMUL;
|
||||
ops : 3;
|
||||
@ -4823,6 +5026,13 @@
|
||||
code : #66#14#32#10#0;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMLA;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#16#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMLA;
|
||||
ops : 3;
|
||||
@ -4830,6 +5040,13 @@
|
||||
code : #66#14#16#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMLS;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#16#10#0;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMLS;
|
||||
ops : 3;
|
||||
@ -4837,6 +5054,13 @@
|
||||
code : #66#14#16#10#0;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMUL;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#32#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNMUL;
|
||||
ops : 3;
|
||||
@ -4844,6 +5068,13 @@
|
||||
code : #66#14#32#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNEG;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#177#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VNEG;
|
||||
ops : 2;
|
||||
@ -4851,6 +5082,13 @@
|
||||
code : #66#14#177#10#64;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSQRT;
|
||||
ops : 2;
|
||||
optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #146#238#177#10#192;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSQRT;
|
||||
ops : 2;
|
||||
@ -4858,6 +5096,13 @@
|
||||
code : #66#14#177#10#192;
|
||||
flags : if_arm32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSUB;
|
||||
ops : 3;
|
||||
optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
|
||||
code : #146#238#48#10#64;
|
||||
flags : if_thumb32 or if_vfpv2
|
||||
),
|
||||
(
|
||||
opcode : A_VSUB;
|
||||
ops : 3;
|
||||
@ -4932,13 +5177,20 @@
|
||||
opcode : A_SVC;
|
||||
ops : 1;
|
||||
optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #97#223#0;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_SVC;
|
||||
ops : 1;
|
||||
optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #2#15;
|
||||
flags : if_arm32 or if_armv4
|
||||
),
|
||||
(
|
||||
opcode : A_SVC;
|
||||
ops : 1;
|
||||
optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #2#15;
|
||||
flags : if_arm32 or if_armv4
|
||||
),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user