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* reduced register pressure when indexing arrays with regvars (regvar
no longer needs to be copied to a temporary register if it isn't
modified)
git-svn-id: trunk@11777 -
This commit is contained in:
Jonas Maebe
parent
2e89b30e86
commit
4971e432de
@ -40,7 +40,7 @@ interface
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end;
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ti386vecnode = class(tcgvecnode)
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procedure update_reference_reg_mul(reg:tregister;l:aint);override;
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procedure update_reference_reg_mul(maybe_const_reg:tregister;l:aint);override;
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procedure pass_generate_code;override;
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end;
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@ -84,7 +84,15 @@ implementation
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TI386VECNODE
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*****************************************************************************}
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procedure ti386vecnode.update_reference_reg_mul(reg:tregister;l:aint);
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{ this routine must, like any other routine, not change the contents }
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{ of base/index registers of references, as these may be regvars. }
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{ The register allocator can coalesce one LOC_REGISTER being moved }
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{ into another (as their live ranges won't overlap), but not a }
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{ LOC_CREGISTER moved into a LOC_(C)REGISTER most of the time (as }
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{ the live range of the LOC_CREGISTER will most likely overlap the }
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{ the live range of the target LOC_(C)REGISTER) }
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{ The passed register may be a LOC_CREGISTER as well. }
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procedure ti386vecnode.update_reference_reg_mul(maybe_const_reg:tregister;l:aint);
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var
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l2 : integer;
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hreg : tregister;
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@ -96,32 +104,42 @@ implementation
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end
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else if location.reference.base=NR_NO then
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begin
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if (location.reference.scalefactor > 1) then
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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case location.reference.scalefactor of
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2 : cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,1,location.reference.index);
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4 : cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,2,location.reference.index);
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8 : cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,3,location.reference.index);
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0,1 : hreg:=location.reference.index;
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2 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,1,location.reference.index,hreg);
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4 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,2,location.reference.index,hreg);
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8 : cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,3,location.reference.index,hreg);
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else
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internalerror(2008091401);
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end;
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location.reference.base:=location.reference.index;
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location.reference.base:=hreg;
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end
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else
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begin
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hreg := cg.getaddressregister(current_asmdata.CurrAsmList);
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,location.reference,hreg);
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reference_reset_base(location.reference,hreg,0);
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end;
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{ insert the new index register and scalefactor or
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do the multiplication manual }
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case l of
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1,2,4,8 : location.reference.scalefactor:=l;
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1,2,4,8 :
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begin
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location.reference.scalefactor:=l;
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hreg:=maybe_const_reg;
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end;
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else
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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if ispowerof2(l,l2) then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,l2,reg)
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,l2,maybe_const_reg,hreg)
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else
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,reg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,maybe_const_reg,hreg);
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end;
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end;
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location.reference.index:=reg;
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location.reference.index:=hreg;
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end;
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@ -66,8 +66,8 @@ interface
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This routine should update location.reference correctly,
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so it points to the correct address.
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}
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procedure update_reference_reg_mul(reg:tregister;l:aint);virtual;
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procedure update_reference_reg_packed(reg:tregister;l:aint);virtual;
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procedure update_reference_reg_mul(maybe_const_reg:tregister;l:aint);virtual;
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procedure update_reference_reg_packed(maybe_const_reg:tregister;l:aint);virtual;
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procedure second_wideansistring;virtual;
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procedure second_dynamicarray;virtual;
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public
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@ -453,39 +453,44 @@ implementation
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end;
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procedure tcgvecnode.update_reference_reg_mul(reg:tregister;l:aint);
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{ this routine must, like any other routine, not change the contents }
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{ of base/index registers of references, as these may be regvars. }
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{ The register allocator can coalesce one LOC_REGISTER being moved }
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{ into another (as their live ranges won't overlap), but not a }
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{ LOC_CREGISTER moved into a LOC_(C)REGISTER most of the time (as }
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{ the live range of the LOC_CREGISTER will most likely overlap the }
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{ the live range of the target LOC_(C)REGISTER) }
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{ The passed register may be a LOC_CREGISTER as well. }
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procedure tcgvecnode.update_reference_reg_mul(maybe_const_reg:tregister;l:aint);
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var
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hreg: tregister;
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begin
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if l<>1 then
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,maybe_const_reg,hreg);
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maybe_const_reg:=hreg;
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end;
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if location.reference.base=NR_NO then
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begin
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if l<>1 then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,reg);
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location.reference.base:=reg;
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end
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location.reference.base:=maybe_const_reg
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else if location.reference.index=NR_NO then
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begin
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if l<>1 then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,reg);
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location.reference.index:=reg;
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end
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location.reference.index:=maybe_const_reg
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else
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begin
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hreg := cg.getaddressregister(current_asmdata.CurrAsmList);
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,location.reference,hreg);
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reference_reset_base(location.reference,hreg,0);
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{ insert new index register }
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if l<>1 then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,reg);
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location.reference.index:=reg;
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location.reference.index:=maybe_const_reg;
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end;
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end;
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procedure tcgvecnode.update_reference_reg_packed(reg:tregister;l:aint);
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{ see remarks for tcgvecnode.update_reference_reg_mul above }
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procedure tcgvecnode.update_reference_reg_packed(maybe_const_reg:tregister;l:aint);
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var
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sref: tsubsetreference;
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offsetreg: tregister;
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offsetreg, hreg: tregister;
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alignpower: aint;
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temp : longint;
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begin
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@ -496,21 +501,22 @@ implementation
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(ispowerof2(l div 8,temp) or
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not is_ordinal(resultdef)) then
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begin
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update_reference_reg_mul(reg,l div 8);
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update_reference_reg_mul(maybe_const_reg,l div 8);
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exit;
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end;
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if (l > 8*sizeof(aint)) then
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internalerror(200608051);
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sref.ref := location.reference;
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offsetreg := cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,tarraydef(left.resultdef).lowrange,reg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_INT,l,reg);
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hreg := cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,tarraydef(left.resultdef).lowrange,maybe_const_reg,hreg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_INT,l,hreg);
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{ keep alignment for index }
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sref.ref.alignment := left.resultdef.alignment;
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if not ispowerof2(sref.ref.alignment,temp) then
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internalerror(2006081201);
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alignpower:=temp;
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_ADDR,3+alignpower,reg,offsetreg);
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offsetreg := cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_ADDR,3+alignpower,hreg,offsetreg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,alignpower,offsetreg);
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if (sref.ref.base = NR_NO) then
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sref.ref.base := offsetreg
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@ -521,8 +527,8 @@ implementation
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_ADDR,sref.ref.base,offsetreg);
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sref.ref.base := offsetreg;
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end;
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_INT,(1 shl (3+alignpower))-1,reg);
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sref.bitindexreg := reg;
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_INT,(1 shl (3+alignpower))-1,hreg);
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sref.bitindexreg := hreg;
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sref.startbit := 0;
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sref.bitlen := resultdef.packedbitsize;
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if (left.location.loc = LOC_REFERENCE) then
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@ -900,7 +906,7 @@ implementation
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secondpass(right);
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{ if mulsize = 1, we won't have to modify the index }
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location_force_reg(current_asmdata.CurrAsmList,right.location,OS_ADDR,not is_packed_array(left.resultdef) and (mulsize = 1) );
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location_force_reg(current_asmdata.CurrAsmList,right.location,OS_ADDR,true);
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if isjump then
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begin
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