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move currentregloc setting to ncgutil to avoid sysym unit ependency in aasmtai unit
git-svn-id: trunk@22513 -
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parent
420cd9bd27
commit
4b7a6ecc14
@ -833,7 +833,6 @@ implementation
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uses
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uses
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SysUtils,
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SysUtils,
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verbose,
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verbose,
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symsym,
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globals;
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globals;
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const
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const
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@ -926,9 +925,7 @@ implementation
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newlocation:=loc;
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newlocation:=loc;
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newlocationhi:=NR_NO;
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newlocationhi:=NR_NO;
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varsym:=sym;
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varsym:=sym;
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oldlocation:=tabstractnormalvarsym(sym).currentregloc.register;
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oldlocationhi:=NR_NO;
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oldlocationhi:=NR_NO;
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tabstractnormalvarsym(sym).currentregloc.register:=newlocation;
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end;
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end;
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@ -939,10 +936,6 @@ implementation
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newlocation:=loc;
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newlocation:=loc;
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newlocationhi:=lochi;
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newlocationhi:=lochi;
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varsym:=sym;
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varsym:=sym;
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oldlocation:=tabstractnormalvarsym(sym).currentregloc.register;
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oldlocationhi:=tabstractnormalvarsym(sym).currentregloc.registerhi;
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tabstractnormalvarsym(sym).currentregloc.register:=newlocation;
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tabstractnormalvarsym(sym).currentregloc.registerHI:=newlocationHI;
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end;
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end;
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@ -954,10 +947,6 @@ implementation
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newlocation:=loc;
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newlocation:=loc;
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newlocationhi:=lochi;
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newlocationhi:=lochi;
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varsym:=sym;
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varsym:=sym;
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oldlocation:=tabstractnormalvarsym(sym).currentregloc.register;
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oldlocationhi:=tabstractnormalvarsym(sym).currentregloc.registerhi;
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tabstractnormalvarsym(sym).currentregloc.register:=newlocation;
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tabstractnormalvarsym(sym).currentregloc.registerHI:=newlocationHI;
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end;
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end;
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{$endif cpu64bitalu}
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{$endif cpu64bitalu}
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@ -1814,6 +1814,7 @@ implementation
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procedure maybechangeloadnodereg(list: TAsmList; var n: tnode; reload: boolean);
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procedure maybechangeloadnodereg(list: TAsmList; var n: tnode; reload: boolean);
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var
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var
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rr: treplaceregrec;
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rr: treplaceregrec;
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varloc : tai_varloc;
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begin
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begin
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{$ifdef jvm}
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{$ifdef jvm}
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exit;
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exit;
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@ -1906,7 +1907,14 @@ implementation
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if assigned(rr.sym) and
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if assigned(rr.sym) and
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((rr.sym.currentregloc.register<>rr.new) or
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((rr.sym.currentregloc.register<>rr.new) or
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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list.concat(tai_varloc.create128(rr.sym,rr.new,rr.newhi));
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begin
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varloc:=tai_varloc.create128(rr.sym,rr.new,rr.newhi);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
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rr.sym.currentregloc.register:=rr.new;
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rr.sym.currentregloc.registerHI:=rr.newhi;
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list.concat(varloc);
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end;
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end
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end
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else
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else
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{$else cpu64bitalu}
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{$else cpu64bitalu}
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@ -1917,14 +1925,26 @@ implementation
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if assigned(rr.sym) and
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if assigned(rr.sym) and
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((rr.sym.currentregloc.register<>rr.new) or
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((rr.sym.currentregloc.register<>rr.new) or
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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list.concat(tai_varloc.create64(rr.sym,rr.new,rr.newhi));
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begin
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varloc:=tai_varloc.create64(rr.sym,rr.new,rr.newhi);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
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rr.sym.currentregloc.register:=rr.new;
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rr.sym.currentregloc.registerHI:=rr.newhi;
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list.concat(varloc);
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end;
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end
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end
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else
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else
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{$endif cpu64bitalu}
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{$endif cpu64bitalu}
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begin
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begin
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n.location.register := rr.new;
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n.location.register := rr.new;
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if assigned(rr.sym) and (rr.sym.currentregloc.register<>rr.new) then
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if assigned(rr.sym) and (rr.sym.currentregloc.register<>rr.new) then
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list.concat(tai_varloc.create(rr.sym,rr.new));
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begin
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varloc:=tai_varloc.create(rr.sym,rr.new);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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rr.sym.currentregloc.register:=rr.new;
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list.concat(varloc);
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end;
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end;
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end;
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end;
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end;
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