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* fpcr and fpsr are 64 bit on aarch64

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git-svn-id: trunk@49346 -
This commit is contained in:
florian 2021-05-08 20:10:14 +00:00
parent ac9d2b3cc5
commit 4de8ca8393
1 changed files with 6 additions and 6 deletions
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12
rtl/aarch64/aarch64.inc
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@ -33,25 +33,25 @@ const
fpu_exception_mask = fpu_ioe or fpu_dze or fpu_ofe or fpu_ufe or fpu_ixe or fpu_ide; fpu_exception_mask = fpu_ioe or fpu_dze or fpu_ofe or fpu_ufe or fpu_ixe or fpu_ide;
fpu_exception_mask_to_status_mask_shift = 8; fpu_exception_mask_to_status_mask_shift = 8;
function getfpcr: dword; nostackframe; assembler; function getfpcr: qword; nostackframe; assembler;
asm asm
mrs x0,fpcr mrs x0,fpcr
end; end;
procedure setfpcr(val: dword); nostackframe; assembler; procedure setfpcr(val: qword); nostackframe; assembler;
asm asm
msr fpcr,x0 msr fpcr,x0
end; end;
function getfpsr: dword; nostackframe; assembler; function getfpsr: qword; nostackframe; assembler;
asm asm
mrs x0,fpsr mrs x0,fpsr
end; end;
procedure setfpsr(val: dword); nostackframe; assembler; procedure setfpsr(val: qword); nostackframe; assembler;
asm asm
msr fpsr, x0 msr fpsr, x0
end; end;
@ -69,7 +69,7 @@ const
procedure RaisePendingExceptions; procedure RaisePendingExceptions;
var var
fpsr : dword; fpsr : qword;
f: TFPUException; f: TFPUException;
begin begin
fpsr:=getfpsr; fpsr:=getfpsr;
@ -96,7 +96,7 @@ procedure RaisePendingExceptions;
exceptions are not supported } exceptions are not supported }
procedure fpc_throwfpuexception;[public,alias:'FPC_THROWFPUEXCEPTION']; procedure fpc_throwfpuexception;[public,alias:'FPC_THROWFPUEXCEPTION'];
var var
fpsr : dword; fpsr : qword;
f: TFPUException; f: TFPUException;
begin begin
{ at this point, we know already, that an exception will be risen } { at this point, we know already, that an exception will be risen }