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* MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake).

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+ Spilling for SEB and SEH
* Another attempt to get spilling of 3-operand form DIV/DIVU be done correctly.

git-svn-id: trunk@28588 -
This commit is contained in:
sergei 2014-09-03 19:57:46 +00:00
parent 406a678223
commit 4e2fb9d28b
1 changed files with 15 additions and 6 deletions
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21
compiler/mips/aasmcpu.pas
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@ -33,9 +33,9 @@ uses
const
{ "mov reg,reg" source operand number }
O_MOV_SOURCE = 0;
O_MOV_SOURCE = 1;
{ "mov reg,reg" source operand number }
O_MOV_DEST = 1;
O_MOV_DEST = 0;
type
{ taicpu }
@ -401,13 +401,22 @@ end;
A_SNE,
A_EXT,
A_INS,
A_MFC0];
A_MFC0,
A_SEB,
A_SEH];
begin
result := operand_read;
if opcode in op_write_set then
if opnr = 0 then
result := operand_write;
case opcode of
A_DIV, { these have 3 operands if used as macros }
A_DIVU:
if (ops=3) and (opnr=0) then
result:=operand_write;
else
if opcode in op_write_set then
if opnr = 0 then
result := operand_write;
end;
end;