paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-09-13 10:29:17 +02:00
Code Issues Packages Projects Releases Wiki Activity

+ allocate and free the flags register (when necessary), when generating code

Browse Source 
for OP_SHR,OP_SHL and OP_SAR in tcg64f8086.a_op64_const_reg

git-svn-id: trunk@36021 -
This commit is contained in:
nickysn 2017-04-30 01:25:54 +00:00
parent a25912da0d
commit 4e4e5d6d07
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
compiler/i8086/cgcpu.pas
View File

@ -3010,17 +3010,21 @@ unit cgcpu;
case op of
OP_SHL:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
list.concat(taicpu.op_const_reg(A_SHL,S_W,1,reg.reglo));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reghi)));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SHR,OP_SAR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
cg.a_op_const_reg(list,op,OS_16,1,GetNextReg(reg.reghi));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reglo));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
end;
2..15:
@ -3032,17 +3036,21 @@ unit cgcpu;
case op of
OP_SHL:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
list.concat(taicpu.op_const_reg(A_SHL,S_W,1,reg.reglo));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reghi)));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SHR,OP_SAR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
cg.a_op_const_reg(list,op,OS_16,1,GetNextReg(reg.reghi));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reglo));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
end;
ai:=Taicpu.Op_Sym(A_LOOP,S_W,loop_start);
@ -3079,15 +3087,19 @@ unit cgcpu;
case op of
OP_SHL:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
list.concat(taicpu.op_const_reg(A_SHL,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reghi)));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SHR,OP_SAR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
cg.a_op_const_reg(list,op,OS_16,1,reg.reghi);
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reglo));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
end;
end;
@ -3123,15 +3135,19 @@ unit cgcpu;
case op of
OP_SHL:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
list.concat(taicpu.op_const_reg(A_SHL,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,reg.reghi));
list.concat(taicpu.op_const_reg(A_RCL,S_W,1,GetNextReg(reg.reghi)));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SHR,OP_SAR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
cg.a_op_const_reg(list,op,OS_16,1,reg.reghi);
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,GetNextReg(reg.reglo)));
list.concat(taicpu.op_const_reg(A_RCR,S_W,1,reg.reglo));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
end;
ai:=Taicpu.Op_Sym(A_LOOP,S_W,loop_start);