diff --git a/compiler/i386/i386prop.inc b/compiler/i386/i386prop.inc
index 1dd8320b36..c9a113a76a 100644
--- a/compiler/i386/i386prop.inc
+++ b/compiler/i386/i386prop.inc
@@ -423,7 +423,7 @@
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
-(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_WOp2, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
@@ -540,7 +540,7 @@
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
-(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_WOp2, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
 (Ch: (Ch_All, Ch_None, Ch_None)),
diff --git a/compiler/i386/i386tab.inc b/compiler/i386/i386tab.inc
index 073a4fdc8a..5e17e7ee02 100644
--- a/compiler/i386/i386tab.inc
+++ b/compiler/i386/i386tab.inc
@@ -8852,7 +8852,7 @@
     opcode  : A_CVTSI2SD;
     ops     : 2;
     optypes : (ot_xmmreg,ot_memory,ot_none);
-    code    : #193#1#242#211#2#15#42#72;
+    code    : #193#1#242#209#2#15#42#72;
     flags   : if_willamette or if_sse2
   ),
   (
diff --git a/compiler/x86/aasmcpu.pas b/compiler/x86/aasmcpu.pas
index 5d5427b311..8967d4a0bd 100644
--- a/compiler/x86/aasmcpu.pas
+++ b/compiler/x86/aasmcpu.pas
@@ -2351,7 +2351,8 @@ implementation
                  (oper[1]^.typ=top_reg) and
                  (oper[0]^.reg=oper[1]^.reg)
                 ) or
-                (((opcode=A_MOVSS) or (opcode=A_MOVSD) or (opcode=A_MOVQ)) and
+                (((opcode=A_MOVSS) or (opcode=A_MOVSD) or (opcode=A_MOVQ) or
+                  (opcode=A_MOVAPS) or (OPCODE=A_MOVAPD)) and
                  (regtype = R_MMREGISTER) and
                  (ops=2) and
                  (oper[0]^.typ=top_reg) and
diff --git a/compiler/x86/cgx86.pas b/compiler/x86/cgx86.pas
index 3e83946400..cac2db6bee 100644
--- a/compiler/x86/cgx86.pas
+++ b/compiler/x86/cgx86.pas
@@ -898,7 +898,15 @@ unit cgx86;
         if shuffle=nil then
           begin
             if fromsize=tosize then
-              instr:=taicpu.op_reg_reg(A_MOVAPS,S_NO,reg1,reg2)
+              { needs correct size in case of spilling }
+              case fromsize of
+                OS_F32:
+                  instr:=taicpu.op_reg_reg(A_MOVAPS,S_NO,reg1,reg2);
+                OS_F64:
+                  instr:=taicpu.op_reg_reg(A_MOVAPD,S_NO,reg1,reg2);
+                else
+                  internalerror(2006091201);
+              end
             else
               internalerror(200312202);
           end
diff --git a/compiler/x86/rgx86.pas b/compiler/x86/rgx86.pas
index d2681657cc..88de47e33e 100644
--- a/compiler/x86/rgx86.pas
+++ b/compiler/x86/rgx86.pas
@@ -223,7 +223,9 @@ implementation
                 { memory locations aren't guaranteed to be aligned }
                 case opcode of
                   A_MOVAPS:
-                    opcode:=A_MOVQ;
+                    opcode:=A_MOVSS;
+                  A_MOVAPD:
+                    opcode:=A_MOVSD;
                 end;
                 result:=true;
               end;
diff --git a/compiler/x86/x86ins.dat b/compiler/x86/x86ins.dat
index bfbba0eb2e..18eb4c0197 100644
--- a/compiler/x86/x86ins.dat
+++ b/compiler/x86/x86ins.dat
@@ -2343,7 +2343,7 @@ xmmreg,mem            \301\333\2\x0F\x5D\110          KATMAI,SSE
 xmmreg,xmmreg         \333\2\x0F\x5D\110              KATMAI,SSE
 
 [MOVAPS]
-(Ch_All, Ch_None, Ch_None)
+(Ch_ROp1, Ch_WOp2, Ch_None)
 xmmreg,mem            \301\2\x0F\x28\110              KATMAI,SSE
 mem,xmmreg            \300\2\x0F\x29\101              KATMAI,SSE
 xmmreg,xmmreg         \2\x0F\x28\110                  KATMAI,SSE
@@ -2971,7 +2971,7 @@ xmmreg,xmmreg           \3\xF2\x0F\x5D\110              WILLAMETTE,SSE2
 xmmreg,mem              \301\1\xF2\323\2\x0F\x5D\110    WILLAMETTE,SSE2
 
 [MOVAPD]
-(Ch_All, Ch_None, Ch_None)
+(Ch_ROp1, Ch_WOp2, Ch_None)
 xmmreg,xmmreg           \3\x66\x0F\x28\110              WILLAMETTE,SSE2
 xmmreg,xmmreg           \3\x66\x0F\x29\110              WILLAMETTE,SSE2
 mem,xmmreg              \300\1\x66\323\2\x0F\x29\101    WILLAMETTE,SSE2,SM