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Use same features for riscv32 as for arm and xtensa CPUs

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This commit is contained in:
Pierre Muller 2023-05-23 22:38:54 +02:00
parent a75a5f9432
commit 53d273692a
1 changed files with 1 additions and 0 deletions
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rtl/freertos/system.cfg
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@ -230,6 +230,7 @@
-SfCOMMANDARGS
-SfRANDOM
-SfRESOURCES
-SfPROCESSES
#endif CPURISCV32
#ifdef CPURISCV64