paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-08-15 06:29:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

* fixed spilling

Browse Source 
* fixed register assignment for instructions requiring a register>R15

git-svn-id: branches/avr@17046 -
This commit is contained in:
florian 2011-02-27 21:10:31 +00:00
parent 93e72b7e8a
commit 53ee505d84
2 changed files with 78 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
compiler/avr/aasmcpu.pas
View File

@ -209,14 +209,14 @@ implementation
function taicpu.spilling_get_operation_type(opnr: longint): topertype; function taicpu.spilling_get_operation_type(opnr: longint): topertype;
begin begin
result := operand_read; result:=operand_read;
case opcode of case opcode of
A_CP,A_CPC,A_CPI : A_CP,A_CPC,A_CPI :
; ;
else else
begin begin
if opnr=ops-1 then if (opnr=0) then
result := operand_write; result:=operand_write;
end; end;
end; end;
end; end;
@ -226,9 +226,15 @@ implementation
begin begin
case getregtype(r) of case getregtype(r) of
R_INTREGISTER : R_INTREGISTER :
result:=taicpu.op_ref_reg(A_LD,ref,r); if ref.offset<>0 then
result:=taicpu.op_reg_ref(A_LDD,r,ref)
else
result:=taicpu.op_reg_ref(A_LD,r,ref);
R_ADDRESSREGISTER : R_ADDRESSREGISTER :
result:=taicpu.op_ref_reg(A_LD,ref,r); if ref.offset<>0 then
result:=taicpu.op_reg_ref(A_LDD,r,ref)
else
result:=taicpu.op_reg_ref(A_LD,r,ref);
else else
internalerror(200401041); internalerror(200401041);
end; end;
@ -239,9 +245,15 @@ implementation
begin begin
case getregtype(r) of case getregtype(r) of
R_INTREGISTER : R_INTREGISTER :
result:=taicpu.op_reg_ref(A_ST,r,ref); if ref.offset<>0 then
result:=taicpu.op_ref_reg(A_STD,ref,r)
else
result:=taicpu.op_ref_reg(A_ST,ref,r);
R_ADDRESSREGISTER : R_ADDRESSREGISTER :
result:=taicpu.op_reg_ref(A_ST,r,ref); if ref.offset<>0 then
result:=taicpu.op_ref_reg(A_STD,ref,r)
else
result:=taicpu.op_ref_reg(A_ST,ref,r);
else else
internalerror(200401041); internalerror(200401041);
end; end;

60
compiler/avr/rgcpu.pas
View File

@ -87,28 +87,80 @@ unit rgcpu;
end; end;
procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister); procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
var
helpins : tai;
tmpref : treference;
helplist : TAsmList;
hreg : tregister;
begin begin
if abs(spilltemp.offset)>63 then
begin
helplist:=TAsmList.create;
helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
reference_reset_base(tmpref,NR_R26,0,1);
helpins:=spilling_create_load(tmpref,tempreg);
helplist.concat(helpins);
list.insertlistafter(pos,helplist);
helplist.free;
end
else
inherited do_spill_read(list,pos,spilltemp,tempreg); inherited do_spill_read(list,pos,spilltemp,tempreg);
end; end;
procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister); procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
var
tmpref : treference;
helplist : TAsmList;
hreg : tregister;
begin begin
if abs(spilltemp.offset)>63 then
begin
helplist:=TAsmList.create;
helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
reference_reset_base(tmpref,NR_R26,0,1);
helplist.concat(spilling_create_store(tempreg,tmpref));
list.insertlistafter(pos,helplist);
helplist.free;
end
else
inherited do_spill_written(list,pos,spilltemp,tempreg); inherited do_spill_written(list,pos,spilltemp,tempreg);
end; end;
procedure trgintcpu.add_cpu_interferences(p : tai); procedure trgintcpu.add_cpu_interferences(p : tai);
var var
r : tregister; r : tsuperregister;
begin begin
if p.typ=ait_instruction then if p.typ=ait_instruction then
begin begin
case taicpu(p).opcode of case taicpu(p).opcode of
A_LD: A_CPI,
; A_ANDI,
A_ORI,
A_SUBI,
A_SBCI,
A_LDI:
for r:=RS_R0 to RS_R15 do
add_edge(r,GetSupReg(taicpu(p).oper[0]^.reg));
A_MULS:
begin
for r:=RS_R0 to RS_R15 do
add_edge(r,GetSupReg(taicpu(p).oper[0]^.reg));
for r:=RS_R0 to RS_R15 do
add_edge(r,GetSupReg(taicpu(p).oper[1]^.reg));
end;
end; end;
end; end;
end; end;