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https://gitlab.com/freepascal.org/fpc/source.git
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* call by register now also takes care of the TOC and environment pointer
* first "optimize for size"-optimization git-svn-id: trunk@1593 -
This commit is contained in:
tom_at_work
parent
58582a44a9
commit
5520442fc4
@ -50,8 +50,6 @@ type
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paraloc: tcgpara); override;
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procedure a_call_name(list: taasmoutput; const s: string); override;
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procedure a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean);
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procedure a_call_reg(list: taasmoutput; reg: tregister); override;
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procedure a_op_const_reg(list: taasmoutput; Op: TOpCG; size: TCGSize; a:
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@ -67,8 +65,11 @@ type
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{ move instructions }
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procedure a_load_const_reg(list: taasmoutput; size: tcgsize; a: aint; reg:
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tregister); override;
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{ stores the contents of register reg to the memory location described by
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ref }
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procedure a_load_reg_ref(list: taasmoutput; fromsize, tosize: tcgsize; reg:
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tregister; const ref: treference); override;
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{ loads the memory pointed to by ref into register reg }
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procedure a_load_ref_reg(list: taasmoutput; fromsize, tosize: tcgsize; const
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Ref: treference; reg: tregister); override;
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procedure a_load_reg_reg(list: taasmoutput; fromsize, tosize: tcgsize; reg1,
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@ -77,6 +78,7 @@ type
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{ fpu move instructions }
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procedure a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2:
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tregister); override;
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procedure a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref:
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treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg:
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@ -150,6 +152,8 @@ type
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{ returns true if the offset of the given reference can not be represented by a 16 bit
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immediate as required by some PowerPC instructions }
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function hasLargeOffset(const ref : TReference) : Boolean; inline;
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procedure a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean; addNOP : boolean);
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end;
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const
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@ -258,10 +262,9 @@ begin
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else
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internalerror(2002072801);
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end;
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LOC_VOID:
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begin
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// nothing to do
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end;
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LOC_VOID:
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{ nothing to do }
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;
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else
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internalerror(2002081103);
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end;
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@ -300,17 +303,17 @@ end;
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procedure tcgppc.a_call_name(list: taasmoutput; const s: string);
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begin
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a_call_name_direct(list, s, true);
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a_call_name_direct(list, s, true, true);
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end;
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procedure tcgppc.a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean);
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procedure tcgppc.a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean; addNOP : boolean);
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begin
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if (prependDot) then begin
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s := '.' + s;
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end;
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if (prependDot) then
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s := '.' + s;
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list.concat(taicpu.op_sym(A_BL, objectlibrary.newasmsymbol(s, AB_EXTERNAL,
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AT_FUNCTION)));
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list.concat(taicpu.op_none(A_NOP));
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if (addNOP) then
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list.concat(taicpu.op_none(A_NOP));
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{
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the compiler does not properly set this flag anymore in pass 1, and
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for now we only need it after pass 2 (I hope) (JM)
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@ -324,35 +327,43 @@ end;
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{ calling a procedure by address }
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procedure tcgppc.a_call_reg(list: taasmoutput; reg: tregister);
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var
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tmpreg: tregister;
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tmpref: treference;
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gotref : treference;
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begin
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tmpreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
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if (not (cs_littlesize in aktglobalswitches)) then begin
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{ load actual function entry (reg contains the reference to the function descriptor)
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into R0 }
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reference_reset_base(tmpref, reg, 0);
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a_load_ref_reg(list, OS_ADDR, OS_ADDR, tmpref, NR_R0);
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reference_reset(tmpref);
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tmpref.offset := 0;
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tmpref.base := reg;
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list.concat(taicpu.op_reg_ref(A_LD, tmpreg, tmpref));
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{ save TOC pointer in stackframe }
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reference_reset_base(tmpref, NR_STACK_POINTER_REG, LA_RTOC_ELF);
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a_load_reg_ref(list, OS_ADDR, OS_ADDR, NR_RTOC, tmpref);
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// TODO: GOT change
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{ move actual function pointer to CTR register }
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list.concat(taicpu.op_reg(A_MTCTR, NR_R0));
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// reference_reset(gotref);
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// tmpref.offset := 40;
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// tmpref.base := rg[R_INTREGISTER].getregister(list, NR_STACK_POINTER_REG);
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{ load new TOC pointer from function descriptor into RTOC register }
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reference_reset_base(tmpref, reg, tcgsize2size[OS_ADDR]);
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a_load_ref_reg(list, OS_ADDR, OS_ADDR, tmpref, NR_RTOC);
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// taicpu.op_load_reg_ref(list, OS_INT, OS_INT,
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list.concat(taicpu.op_reg(A_MTCTR, tmpreg));
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{ load new environment pointer from function descriptor into R11 register }
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reference_reset_base(tmpref, reg, 2*tcgsize2size[OS_ADDR]);
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a_load_ref_reg(list, OS_ADDR, OS_ADDR, tmpref, NR_R11);
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{ call function }
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list.concat(taicpu.op_none(A_BCTRL));
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end else begin
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{ call ptrgl helper routine which expects the pointer to the function descriptor
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in R11 }
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a_load_reg_reg(list, OS_ADDR, OS_ADDR, reg, NR_R11);
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a_call_name_direct(list, 'ptrgl', true, false);
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end;
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{ we need to load the old RTOC from stackframe because we changed it}
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reference_reset_base(tmpref, NR_STACK_POINTER_REG, LA_RTOC_ELF);
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a_load_ref_reg(list, OS_ADDR, OS_ADDR, tmpref, NR_RTOC);
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list.concat(taicpu.op_none(A_BCTRL));
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//if target_info.system=system_powerpc_macos then
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// //NOP is not needed here.
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// list.concat(taicpu.op_none(A_NOP));
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include(current_procinfo.flags, pi_do_call);
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end;
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@ -389,7 +400,7 @@ procedure tcgppc.a_load_const_reg(list: taasmoutput; size: TCGSize; a: aint;
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procedure load32bitconstantR0(list : taasmoutput; size : TCGSize; a : longint;
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reg : TRegister);
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begin
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// only 16 bit constant? (-2^15 <= a <= +2^15-1)
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{ only 16 bit constant? (-2^15 <= a <= +2^15-1) }
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if (a >= low(smallint)) and (a <= high(smallint)) then begin
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list.concat(taicpu.op_reg_const(A_LI, reg, smallint(a)));
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end else begin
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@ -474,7 +485,7 @@ procedure tcgppc.a_load_ref_reg(list: taasmoutput; fromsize, tosize: tcgsize;
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const
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LoadInstr: array[OS_8..OS_S64, boolean, boolean] of TAsmOp =
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{ indexed? updating?}
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{ indexed? updating? }
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(((A_LBZ, A_LBZU), (A_LBZX, A_LBZUX)),
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((A_LHZ, A_LHZU), (A_LHZX, A_LHZUX)),
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((A_LWZ, A_LWZU), (A_LWZX, A_LWZUX)),
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@ -493,26 +504,24 @@ var
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ref2: treference;
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begin
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{ TODO: optimize/take into consideration fromsize/tosize. Will }
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{ probably only matter for OS_S8 loads though }
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if not (fromsize in [OS_8, OS_S8, OS_16, OS_S16, OS_32, OS_S32, OS_64, OS_S64]) then
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internalerror(2002090902);
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ref2 := ref;
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fixref(list, ref2, tosize);
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{ the caller is expected to have adjusted the reference already }
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{ in this case }
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{ the caller is expected to have adjusted the reference already
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in this case }
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if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
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fromsize := tosize;
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op := loadinstr[fromsize, ref2.index <> NR_NO, false];
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// there is no LWAU instruction, simulate using ADDI and LWA
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{ there is no LWAU instruction, simulate using ADDI and LWA }
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if (op = A_LWAU) then begin
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list.concat(taicpu.op_reg_reg_const(A_ADDI, reg, reg, ref2.offset));
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ref2.offset := 0;
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op := A_LWA;
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end;
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a_load_store(list, op, reg, ref2);
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// sign extend shortint if necessary, since there is no
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// load instruction that does that automatically (JM)
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{ sign extend shortint if necessary, since there is no
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load instruction that does that automatically (JM) }
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if fromsize = OS_S8 then
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list.concat(taicpu.op_reg_reg(A_EXTSB, reg, reg));
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end;
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@ -573,8 +582,8 @@ var
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ref2: treference;
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begin
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{ several functions call this procedure with OS_32 or OS_64 }
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{ so this makes life easier (FK) }
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{ several functions call this procedure with OS_32 or OS_64
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so this makes life easier (FK) }
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case size of
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OS_32, OS_F32:
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size := OS_F32;
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@ -594,7 +603,7 @@ procedure tcgppc.a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg:
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const
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FpuStoreInstr: array[OS_F32..OS_F64, boolean, boolean] of TAsmOp =
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{ indexed? updating?}
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{ indexed? updating? }
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(((A_STFS, A_STFSU), (A_STFSX, A_STFSUX)),
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((A_STFD, A_STFDU), (A_STFDX, A_STFDUX)));
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var
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@ -635,7 +644,7 @@ var
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begin
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usereg := false;
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if (size in [OS_64, OS_S64]) then begin
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// ts: use register method for 64 bit consts. Sloooooow
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{ ts: use register method for 64 bit consts. Sloooooow }
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usereg := true;
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end else if (size in [OS_32, OS_S32]) then begin
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list.concat(taicpu.op_reg_reg_const(oplo, dst, src, word(a)));
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@ -652,8 +661,8 @@ begin
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end;
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ophi := TOpCG2AsmOpConstHi[op];
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oplo := TOpCG2AsmOpConstLo[op];
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// peephole optimizations for AND, OR, XOR - can't this be done at
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// some higher level, independent of architecture?
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{ peephole optimizations for AND, OR, XOR - can't this be done at
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some higher level, independent of architecture? }
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if (op in [OP_AND, OP_OR, OP_XOR]) then begin
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if (a = 0) then begin
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if op = OP_AND then
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@ -682,8 +691,7 @@ begin
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exit;
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end;
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{ otherwise, the instructions we can generate depend on the }
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{ operation }
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{ otherwise, the instructions we can generate depend on the operation }
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useReg := false;
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case op of
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OP_DIV, OP_IDIV:
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@ -897,8 +905,7 @@ var
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bitvalue: boolean;
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begin
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{ get the bit to extract from the conditional register + its }
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{ requested value (0 or 1) }
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{ get the bit to extract from the conditional register + its requested value (0 or 1) }
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testbit := ((f.cr - RS_CR0) * 4);
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case f.flag of
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F_EQ, F_NE:
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@ -920,8 +927,7 @@ begin
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end;
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{ load the conditional register in the destination reg }
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list.concat(taicpu.op_reg(A_MFCR, reg));
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{ we will move the bit that has to be tested to bit 0 by rotating }
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{ left }
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{ we will move the bit that has to be tested to bit 0 by rotating left }
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testbit := (testbit + 1) and 31;
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{ extract bit }
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list.concat(taicpu.op_reg_reg_const_const_const(
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@ -980,13 +986,13 @@ end;
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procedure tcgppc.g_proc_entry(list: taasmoutput; localsize: longint;
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nostackframe: boolean);
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{ generated the entry code of a procedure/function. Note: localsize is the }
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{ sum of the size necessary for local variables and the maximum possible }
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{ combined size of ALL the parameters of a procedure called by the current }
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{ one. }
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{ This procedure may be called before, as well as after g_return_from_proc }
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{ is called. NOTE registers are not to be allocated through the register }
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{ allocator here, because the register colouring has already occured !! }
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{ generated the entry code of a procedure/function. Note: localsize is the
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sum of the size necessary for local variables and the maximum possible
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combined size of ALL the parameters of a procedure called by the current
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one.
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This procedure may be called before, as well as after g_return_from_proc
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is called. NOTE registers are not to be allocated through the register
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allocator here, because the register colouring has already occured !! }
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var
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firstregfpu, firstreggpr: TSuperRegister;
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href: treference;
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@ -996,34 +1002,34 @@ var
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fprcount, gprcount : aint;
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begin
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{ CR and LR only have to be saved in case they are modified by the current }
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{ procedure, but currently this isn't checked, so save them always }
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{ following is the entry code as described in "Altivec Programming }
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{ Interface Manual", bar the saving of AltiVec registers }
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{ CR and LR only have to be saved in case they are modified by the current
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procedure, but currently this isn't checked, so save them always
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following is the entry code as described in "Altivec Programming
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Interface Manual", bar the saving of AltiVec registers }
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a_reg_alloc(list, NR_STACK_POINTER_REG);
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a_reg_alloc(list, NR_R0);
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calcFirstUsedFPR(firstregfpu, fprcount);
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calcFirstUsedGPR(firstreggpr, gprcount);
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// calculate real stack frame size
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{ calculate real stack frame size }
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localsize := tppcprocinfo(current_procinfo).calc_stackframe_size(
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gprcount, fprcount);
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// determine whether we need to save the link register
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{ determine whether we need to save the link register }
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needslinkreg := ((not (po_assembler in current_procinfo.procdef.procoptions)) and
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(pi_do_call in current_procinfo.flags));
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// move link register to r0
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{ move link register to r0 }
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if (needslinkreg) then begin
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list.concat(taicpu.op_reg(A_MFLR, NR_R0));
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end;
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// save old stack frame pointer
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{ save old stack frame pointer }
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if (localsize > 0) then begin
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a_reg_alloc(list, NR_R12);
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list.concat(taicpu.op_reg_reg(A_MR, NR_R12, NR_STACK_POINTER_REG));
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end;
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// save registers, FPU first, then GPR
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{ save registers, FPU first, then GPR }
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reference_reset_base(href, NR_STACK_POINTER_REG, -8);
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if (fprcount > 0) then begin
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for regcount := RS_F31 downto firstregfpu do begin
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@ -1040,15 +1046,15 @@ begin
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end;
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end;
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// VMX registers not supported by FPC atm
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{ VMX registers not supported by FPC atm }
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// we may need to store R0 (=LR) ourselves
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{ we may need to store R0 (=LR) ourselves }
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if (needslinkreg) then begin
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reference_reset_base(href, NR_STACK_POINTER_REG, LA_LR_ELF);
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list.concat(taicpu.op_reg_ref(A_STD, NR_R0, href));
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end;
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// create stack frame
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{ create stack frame }
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if (not nostackframe) and (localsize > 0) then begin
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if (localsize <= high(smallint)) then begin
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reference_reset_base(href, NR_STACK_POINTER_REG, -localsize);
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@ -1056,10 +1062,10 @@ begin
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end else begin
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reference_reset_base(href, NR_NO, -localsize);
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// use R0 for loading the constant (which is definitely > 32k when entering
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// this branch)
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// inlined because it must not use temp registers because register allocations
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// have already been done :(
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{ use R0 for loading the constant (which is definitely > 32k when entering
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this branch)
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Inlined at this position because it must not use temp registers because
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register allocations have already been done :( }
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{ Code template:
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lis r0,ofs@highest
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ori r0,r0,ofs@higher
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@ -1076,9 +1082,9 @@ begin
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list.concat(taicpu.op_reg_reg_reg(A_STDUX, NR_R1, NR_R1, NR_R0));
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end;
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end;
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// CR register not used by FPC atm
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{ CR register not used by FPC atm }
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// keep R1 allocated???
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{ keep R1 allocated??? }
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a_reg_dealloc(list, NR_R0);
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end;
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@ -1097,26 +1103,26 @@ begin
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calcFirstUsedFPR(firstregfpu, fprcount);
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calcFirstUsedGPR(firstreggpr, gprcount);
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// determine whether we need to restore the link register
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{ determine whether we need to restore the link register }
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needslinkreg := ((not (po_assembler in current_procinfo.procdef.procoptions)) and
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(pi_do_call in current_procinfo.flags));
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// calculate stack frame
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{ calculate stack frame }
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localsize := tppcprocinfo(current_procinfo).calc_stackframe_size(
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gprcount, fprcount);
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// CR register not supported
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{ CR register not supported }
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// restore stack pointer
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{ restore stack pointer }
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if (not nostackframe) and (localsize > 0) then begin
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if (localsize <= high(smallint)) then begin
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list.concat(taicpu.op_reg_reg_const(A_ADDI, NR_STACK_POINTER_REG, NR_STACK_POINTER_REG, localsize));
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end else begin
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reference_reset_base(href, NR_NO, localsize);
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// use R0 for loading the constant (which is definitely > 32k when entering
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// this branch)
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// inlined because it must not use temp registers because register allocations
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// have already been done :(
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{ use R0 for loading the constant (which is definitely > 32k when entering
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this branch)
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Inlined because it must not use temp registers because register allocations
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have already been done :( }
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{ Code template:
|
||||
lis r0,ofs@highest
|
||||
ori r0,ofs@higher
|
||||
@ -1134,7 +1140,7 @@ begin
|
||||
end;
|
||||
end;
|
||||
|
||||
// load registers, FPR first, then GPR
|
||||
{ load registers, FPR first, then GPR }
|
||||
{$note ts:todo change order of loading}
|
||||
reference_reset_base(href, NR_STACK_POINTER_REG, -tcgsize2size[OS_FLOAT]);
|
||||
if (fprcount > 0) then begin
|
||||
@ -1152,16 +1158,16 @@ begin
|
||||
end;
|
||||
end;
|
||||
|
||||
// VMX not supported...
|
||||
{ VMX not supported... }
|
||||
|
||||
// restore LR (if needed)
|
||||
{ restore LR (if needed) }
|
||||
if (needslinkreg) then begin
|
||||
reference_reset_base(href, NR_STACK_POINTER_REG, LA_LR_ELF);
|
||||
list.concat(taicpu.op_reg_ref(A_LD, NR_R0, href));
|
||||
list.concat(taicpu.op_reg(A_MTLR, NR_R0));
|
||||
end;
|
||||
|
||||
// generate return instruction
|
||||
{ generate return instruction }
|
||||
list.concat(taicpu.op_none(A_BLR));
|
||||
end;
|
||||
|
||||
@ -1171,7 +1177,7 @@ procedure tcgppc.a_loadaddr_ref_reg(list: taasmoutput; const ref: treference; r:
|
||||
|
||||
var
|
||||
ref2, tmpref: treference;
|
||||
// register used to construct address
|
||||
{ register used to construct address }
|
||||
tempreg : TRegister;
|
||||
|
||||
begin
|
||||
@ -1185,17 +1191,17 @@ begin
|
||||
tmpref.offset := ref2.offset;
|
||||
tmpref.symbol := ref2.symbol;
|
||||
tmpref.relsymbol := ref2.relsymbol;
|
||||
// load 64 bit reference into r. If the reference already has a base register,
|
||||
// first load the 64 bit value into a temp register, then add it to the result
|
||||
// register rD
|
||||
{ load 64 bit reference into r. If the reference already has a base register,
|
||||
first load the 64 bit value into a temp register, then add it to the result
|
||||
register rD }
|
||||
if (ref2.base <> NR_NO) then begin
|
||||
// already have a base register, so allocate a new one
|
||||
{ already have a base register, so allocate a new one }
|
||||
tempreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
|
||||
end else begin
|
||||
tempreg := r;
|
||||
end;
|
||||
|
||||
// code for loading a reference from a symbol into a register rD.
|
||||
{ code for loading a reference from a symbol into a register rD }
|
||||
(*
|
||||
lis rX,SYM@highest
|
||||
ori rX,SYM@higher
|
||||
@ -1213,8 +1219,8 @@ begin
|
||||
tmpref.refaddr := addr_low;
|
||||
list.concat(taicpu.op_reg_reg_ref(A_ORI, tempreg, tempreg, tmpref));
|
||||
|
||||
// if there's already a base register, add the temp register contents to
|
||||
// the base register
|
||||
{ if there's already a base register, add the temp register contents to
|
||||
the base register }
|
||||
if (ref2.base <> NR_NO) then begin
|
||||
list.concat(taicpu.op_reg_reg_reg(A_ADD, r, tempreg, ref2.base));
|
||||
end;
|
||||
@ -1222,8 +1228,8 @@ begin
|
||||
{ no symbol, but offset <> 0 }
|
||||
if ref2.base <> NR_NO then begin
|
||||
a_op_const_reg_reg(list, OP_ADD, OS_64, ref2.offset, ref2.base, r)
|
||||
{ FixRef makes sure that "(ref.index <> R_NO) and (ref.offset <> 0)" never}
|
||||
{ occurs, so now only ref.offset has to be loaded }
|
||||
{ FixRef makes sure that "(ref.index <> R_NO) and (ref.offset <> 0)" never
|
||||
occurs, so now only ref.offset has to be loaded }
|
||||
end else begin
|
||||
a_load_const_reg(list, OS_64, ref2.offset, r)
|
||||
end;
|
||||
@ -1305,18 +1311,18 @@ begin
|
||||
|
||||
{ generate a loop }
|
||||
if count > 4 then begin
|
||||
{ the offsets are zero after the a_loadaddress_ref_reg and just }
|
||||
{ have to be set to 8. I put an Inc there so debugging may be }
|
||||
{ easier (should offset be different from zero here, it will be }
|
||||
{ easy to notice in the generated assembler }
|
||||
{ the offsets are zero after the a_loadaddress_ref_reg and just
|
||||
have to be set to 8. I put an Inc there so debugging may be
|
||||
easier (should offset be different from zero here, it will be
|
||||
easy to notice in the generated assembler }
|
||||
inc(dst.offset, 8);
|
||||
inc(src.offset, 8);
|
||||
list.concat(taicpu.op_reg_reg_const(A_SUBI, src.base, src.base, 8));
|
||||
list.concat(taicpu.op_reg_reg_const(A_SUBI, dst.base, dst.base, 8));
|
||||
countreg := rg[R_INTREGISTER].getregister(list, R_SUBWHOLE);
|
||||
a_load_const_reg(list, OS_32, count, countreg);
|
||||
{ explicitely allocate R_0 since it can be used safely here }
|
||||
{ (for holding date that's being copied) }
|
||||
{ explicitely allocate R_0 since it can be used safely here
|
||||
(for holding date that's being copied) }
|
||||
a_reg_alloc(list, NR_F0);
|
||||
objectlibrary.getjumplabel(lab);
|
||||
a_label(list, lab);
|
||||
@ -1382,10 +1388,10 @@ begin
|
||||
(torddef(def).typ in [u64bit, u16bit, u32bit, u8bit, uchar,
|
||||
bool8bit, bool16bit, bool32bit]))) then
|
||||
begin
|
||||
// ... instruction setting overflow flag ...
|
||||
// mfxerf R0
|
||||
// mtcrf 128, R0
|
||||
// ble cr0, label
|
||||
{ ... instructions setting overflow flag ...
|
||||
mfxerf R0
|
||||
mtcrf 128, R0
|
||||
ble cr0, label }
|
||||
list.concat(taicpu.op_reg(A_MFXER, NR_R0));
|
||||
list.concat(taicpu.op_const_reg(A_MTCRF, 128, NR_R0));
|
||||
flags.cr := RS_CR0;
|
||||
@ -1426,15 +1432,15 @@ procedure tcgppc.g_intf_wrapper(list: TAAsmoutput; procdef: tprocdef; const
|
||||
{ add support for offsets > 16 bit }
|
||||
internalerror(200510201);
|
||||
list.concat(taicpu.op_reg_ref(A_LD, NR_R11, href));
|
||||
// the loaded reference is a function descriptor reference, so deref again
|
||||
// (at ofs 0 there's the real pointer)
|
||||
{ the loaded reference is a function descriptor reference, so deref again
|
||||
(at ofs 0 there's the real pointer) }
|
||||
{$warning ts:TODO: update GOT reference}
|
||||
reference_reset_base(href, NR_R11, 0);
|
||||
list.concat(taicpu.op_reg_ref(A_LD, NR_R11, href));
|
||||
|
||||
list.concat(taicpu.op_reg(A_MTCTR, NR_R11));
|
||||
list.concat(taicpu.op_none(A_BCTR));
|
||||
// NOP needed for the linker...?
|
||||
{ NOP needed for the linker...? }
|
||||
list.concat(taicpu.op_none(A_NOP));
|
||||
end;
|
||||
|
||||
@ -1464,11 +1470,10 @@ begin
|
||||
{ set param1 interface to self }
|
||||
g_adjust_self_value(list, procdef, ioffset);
|
||||
|
||||
{ case 4 }
|
||||
if po_virtualmethod in procdef.procoptions then begin
|
||||
loadvmttor11;
|
||||
op_onr11methodaddr;
|
||||
end { case 0 } else
|
||||
end else
|
||||
{$note ts:todo add GOT change?? - think not needed :) }
|
||||
list.concat(taicpu.op_sym(A_B,
|
||||
objectlibrary.newasmsymbol('.' + procdef.mangledname, AB_EXTERNAL,
|
||||
|
||||
@ -60,6 +60,22 @@
|
||||
li 3,1
|
||||
sc
|
||||
.endm
|
||||
|
||||
.section ".text"
|
||||
.align 3
|
||||
.globl .ptrgl
|
||||
.ptrgl:
|
||||
ld 0, 0(11)
|
||||
std 2, 40(1)
|
||||
mtctr 0
|
||||
ld 2, 8(11)
|
||||
ld 11, 8(11)
|
||||
bctr
|
||||
.long 0
|
||||
.byte 0, 12, 0, 0, 0, 0, 0, 0
|
||||
.type .ptrgl, @function
|
||||
.size .ptrgl, . - .ptrgl
|
||||
|
||||
/*
|
||||
Main Pascal entry point label (function)
|
||||
*/
|
||||
@ -69,7 +85,7 @@ FUNCTION_PROLOG _start
|
||||
/* Set up an initial stack frame, and clear the LR */
|
||||
clrrdi 1, 1, 5 /* align r1 */
|
||||
li 0, 0
|
||||
stdu 1,-48(1)
|
||||
stdu 1,-128(1)
|
||||
mtlr 0
|
||||
std 0, 0(1) /* r1 = pointer to NULL value */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user