+ created a parseable Z80 instruction description file, very loosely based on x86ins.dat. Parser not

implemented yet, but will be soon.

git-svn-id: branches/z80@44554 -

.gitattributes

@@ -1079,6 +1079,7 @@ compiler/z80/rz80sta.inc svneol=native#text/plain
 compiler/z80/rz80std.inc svneol=native#text/plain
 compiler/z80/rz80sup.inc svneol=native#text/plain
 compiler/z80/symcpu.pas svneol=native#text/plain
+compiler/z80/z80ins.dat svneol=native#text/plain
 compiler/z80/z80reg.dat svneol=native#text/plain
 /fpmake.pp svneol=native#text/plain
 /fpmake_add1.inc svneol=native#text/plain

compiler/z80/z80ins.dat

@@ -0,0 +1,372 @@
+; legend:
+; r      - 8-bit register: A/B/C/D/E/H/L
+; r'     - 8-bit register: A/B/C/D/E/H/L
+; b      - 3-bit immediate value (bit number: [0..7])
+; n      - 8-bit immediate value
+; p      - immediate value in [$00,$08,$10,$18,$20,$28,$30,$38]
+; e      - 8-bit relative jump offset
+; nn     - 16-bit immediate value
+; cc     - condition: NZ/Z/NC/C/PO/PE/P/M
+; C      - condition C
+; NC     - condition NC
+; Z      - condition Z
+; NZ     - condition NZ
+; dd     - 16-bit register pair: BC/DE/HL/SP
+; qq     - 16-bit register pair: BC/DE/HL/AF
+; pp     - 16-bit register pair: BC/DE/IX/SP
+; rr     - 16-bit register pair: BC/DE/IY/SP
+; A      - register A
+; I      - register I
+; R      - register R
+; IX     - register IX
+; IY     - register IY
+; SP     - register SP
+; DE     - 16-bit register pair DE
+; HL     - 16-bit register pair HL
+; AF     - 16-bit register pair AF
+; AF'    - alternate register set, 16-bit register pair AF'
+; (C)    - implied parameter of the IN and OUT instructions
+; (nn)   - memory contents at address (nn = 16-bit immediate address)
+; (BC)   - memory contents at address in register BC
+; (DE)   - memory contents at address in register DE
+; (HL)   - memory contents at address in register HL
+; (SP)   - memory contents at address in register SP
+; (IX+d) - memory contents at address in register IX+d, d is in [-128..127]
+; (IY+d) - memory contents at address in register IX+d, d is in [-128..127]
+
+[ADC]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+HL,dd
+
+[ADD]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+HL,dd
+IX,pp
+IY,rr
+
+[AND]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+
+[BIT]
+b,r
+b,(HL)
+b,(IX+d)
+b,(IY+d)
+
+[CALL]
+nn
+cc,nn
+
+[CCF]
+void
+
+[CP]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+
+[CPD]
+void
+
+[CPDR]
+void
+
+[CPI]
+void
+
+[CPIR]
+void
+
+[CPL]
+void
+
+[DAA]
+void
+
+[DEC]
+r
+(HL)
+(IX+d)
+(IY+d)
+dd
+IX
+IY
+
+[DI]
+void
+
+[DJNZ]
+e
+
+[EI]
+void
+
+[EX]
+DE,HL
+AF,AF'
+(SP),HL
+(SP),IX
+(SP),IY
+
+[EXX]
+void
+
+[HALT]
+void
+
+[IM]
+0
+1
+2
+
+[IN]
+A,(n)
+r,(C)
+
+[INC]
+r
+(HL)
+(IX+d)
+(IY+d)
+dd
+IX
+IY
+
+[IND]
+void
+
+[INDR]
+void
+
+[INI]
+void
+
+[INIR]
+void
+
+[JP]
+nn
+cc,nn
+(HL)
+(IX)
+(IY)
+
+[JR]
+e
+C,e
+NC,e
+Z,e
+NZ,e
+
+[LD]
+r,r'
+r,n
+r,(HL)
+r,(IX+d)
+r,(IY+d)
+(HL),r
+(IX+d),r
+(IY+d),r
+(HL),n
+(IX+d),n
+(IY+d),n
+A,(BC)
+A,(DE)
+A,(nn)
+(BC),A
+(DE),A
+(nn),A
+A,I
+A,R
+I,A
+R,A
+dd,nn
+IX,nn
+IY,nn
+HL,(nn)
+dd,(nn)
+IX,(nn)
+IY,(nn)
+(nn),HL
+(nn),dd
+(nn),IX
+(nn),IY
+SP,HL
+SP,IX
+SP,IY
+
+[LDD]
+void
+
+[LDDR]
+void
+
+[LDI]
+void
+
+[LDIR]
+void
+
+[NEG]
+void
+
+[NOP]
+void
+
+[OR]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+
+[OTDR]
+void
+
+[OTIR]
+void
+
+[OUT]
+(n),A
+(C),r
+
+[OUTD]
+void
+
+[OUTI]
+void
+
+[POP]
+qq
+IX
+IY
+
+[PUSH]
+qq
+IX
+IY
+
+[RES]
+b,r
+b,(HL)
+b,(IX+d)
+b,(IY+d)
+
+[RET]
+void
+cc
+
+[RETI]
+void
+
+[RETN]
+void
+
+[RL]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[RLA]
+void
+
+[RLC]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[RLCA]
+void
+
+[RLD]
+void
+
+[RR]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[RRA]
+void
+
+[RRC]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[RRCA]
+void
+
+[RRD]
+void
+
+[RST]
+p
+
+[SBC]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+HL,dd
+
+[SCF]
+void
+
+[SET]
+b,r
+b,(HL)
+b,(IX+d)
+b,(IY+d)
+
+[SLA]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[SRA]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[SRL]
+r
+(HL)
+(IX+d)
+(IY+d)
+
+[SUB]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+
+[XOR]
+A,r
+A,n
+A,(HL)
+A,(IX+d)
+A,(IY+d)
+