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Fix bug in lui+addi immediate load for spilling code.

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git-svn-id: branches/laksen/riscv_new@39764 -
This commit is contained in:
Jeppe Johansen 2018-09-16 20:51:15 +00:00
parent 74a7963d58
commit 576ef934bd
1 changed files with 2 additions and 2 deletions
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4
compiler/riscv/rgcpu.pas
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@ -67,9 +67,9 @@ unit rgcpu;
hreg:=cg.getintregister(helplist,OS_ADDR);
if (spilltemp.offset and $800)<>0 then
helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF))
helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF))
else
helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF));
helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF));
helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(spilltemp.offset shl 4,4)));
helplist.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,hreg,spilltemp.base));