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* Correct SigContext structures
git-svn-id: trunk@14203 -
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@ -15,48 +15,70 @@
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**********************************************************************}
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const
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FPE_INTDIV = 1;
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FPE_INTOVF = 2;
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FPE_FLTDIV = 3;
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FPE_FLTOVF = 4;
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FPE_FLTUND = 5;
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FPE_FLTRES = 6;
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FPE_FLTINV = 7;
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FPE_FLTSUB = 8;
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procedure SignalToRunerror(sig : longint; SigInfo: PSigInfo; SigContext: PSigContext);public name '_FPC_DEFAULTSIGHANDLER';cdecl;
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var
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res,fpustate : word;
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res : word;
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addr : pointer;
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frame : pointer;
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begin
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res:=0;
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if assigned(sigcontext) then
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begin
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addr := pointer(sigcontext^.uc_mcontext.gregs[REG_PC]);
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frame := pointer(sigcontext^.uc_mcontext.gregs[REG_FP])
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end
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else
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begin
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addr := nil;
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frame := nil;
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end;
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case sig of
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SIGFPE :
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begin
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res:=200;
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(*
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fpustate:=GetFPUState(SigContext^);
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if (FpuState and FPU_All) <> 0 then
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begin
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{ first check the more precise options }
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if (FpuState and FPU_DivisionByZero)<>0 then
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res:=200
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else if (FpuState and FPU_Overflow)<>0 then
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res:=205
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else if (FpuState and FPU_Underflow)<>0 then
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res:=206
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else if (FpuState and FPU_Denormal)<>0 then
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res:=216
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else if (FpuState and (FPU_StackOverflow or FPU_StackUnderflow or FPU_Invalid))<>0 Then
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res:=207
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else
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res:=207; {'Coprocessor Error'}
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end;
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*)
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sysResetFPU;
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begin
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case siginfo^.si_code of
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FPE_INTDIV:
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res:=200;
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FPE_INTOVF:
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res:=205;
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FPE_FLTDIV:
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res:=200;
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FPE_FLTOVF:
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res:=205;
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FPE_FLTUND:
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res:=206;
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else
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res:=207;
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end;
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end;
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SIGILL,
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SIGBUS,
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SIGSEGV :
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res:=216;
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begin
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res:=216;
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end;
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SIGBUS :
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begin
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res:=214;
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end;
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SIGINT:
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res:=217;
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SIGKILL :
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SIGQUIT:
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res:=233;
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end;
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{ give runtime error at the position where the signal was raised }
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reenable_signal(sig);
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{ give runtime error at the position where the signal was raised }
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if res<>0 then
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HandleErrorAddrFrame(res,pointer(SigContext^.eip),pointer(SigContext^.ebp));
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HandleErrorAddrFrame(res,addr,frame);
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end;
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@ -1,9 +1,12 @@
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{
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This file is part of the Free Pascal run time library.
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Copyright (c) 1999-2000 by Jonas Maebe,
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Copyright (c) 2009 by Pierre Muller,
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member of the Free Pascal development team.
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Sigcontext and Sigaction
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Sigcontext and Sigaction for amd64/i386 CPUs
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Adapted from
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http://cvs.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/intel/sys/regset.h
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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@ -16,33 +19,233 @@
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{$packrecords C}
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{$packrecords C}
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const
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{ i386/amd64 definition }
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{
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#if defined(__amd64)
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#define _NGREG 28
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#else
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#define _NGREG 19
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#endif
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}
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{$ifdef x86_64 }
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_NGREG = 28;
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{$else i386 }
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_NGREG = 19;
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{$endif i386 }
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_NGREG32 = 19;
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_NGREG64 = 28;
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{$ifdef x86_64}
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(* AMD64 layout
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#define REG_GSBASE 27
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#define REG_FSBASE 26
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#define REG_DS 25
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#define REG_ES 24
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#define REG_GS 23
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#define REG_FS 22
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#define REG_SS 21
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#define REG_RSP 20
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#define REG_RFL 19
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#define REG_CS 18
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#define REG_RIP 17
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#define REG_ERR 16
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#define REG_TRAPNO 15
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#define REG_RAX 14
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#define REG_RCX 13
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#define REG_RDX 12
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#define REG_RBX 11
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#define REG_RBP 10
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#define REG_RSI 9
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#define REG_RDI 8
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#define REG_R8 7
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#define REG_R9 6
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#define REG_R10 5
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#define REG_R11 4
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#define REG_R12 3
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#define REG_R13 2
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#define REG_R14 1
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#define REG_R15 0
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*)
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REG_R15 = 0;
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REG_R14 = 1;
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REG_R13 = 2;
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REG_R12 = 3;
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REG_R11 = 4;
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REG_R10 = 5;
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REG_R9 = 6;
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REG_R8 = 7;
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REG_RDI = 8;
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REG_RSI = 9;
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REG_RBP = 10;
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REG_RBX = 11;
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REG_RDX = 12;
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REG_RCX = 13;
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REG_RAX = 14;
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REG_TRAPNO = 15;
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REG_ERR = 16;
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REG_RIP = 17;
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REG_CS = 18;
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REG_RFL = 19;
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REG_RSP = 20;
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REG_SS = 21;
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REG_FS = 22;
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REG_GS = 23;
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REG_ES = 24;
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REG_DS = 25;
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REG_FSBASE = 26;
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REG_GSBASE = 27;
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{$else i386}
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(* I386 layout
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#define SS 18 /* only stored on a privilege transition */
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#define UESP 17 /* only stored on a privilege transition */
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#define EFL 16
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#define CS 15
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#define EIP 14
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#define ERR 13
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#define TRAPNO 12
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#define EAX 11
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#define ECX 10
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#define EDX 9
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#define EBX 8
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#define ESP 7
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#define EBP 6
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#define ESI 5
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#define EDI 4
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#define DS 3
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#define ES 2
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#define FS 1
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#define GS 0
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*)
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REG_GS = 0;
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REG_FS = 1;
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REG_ES = 2;
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REG_DS = 3;
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REG_EDI = 4;
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REG_ESI = 5;
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REG_EBP = 6;
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REG_ESP = 7;
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REG_EBX = 8;
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REG_EDX = 9;
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REG_ECX = 10;
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REG_EAX = 11;
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REG_TRAPNO = 12;
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REG_ERR = 13;
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REG_EIP = 14;
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REG_CS = 15;
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REG_EFL = 16;
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REG_UESP = 17; (* only stored on a privilege transition *)
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REG_SS = 18; (* only stored on a privilege transition *)
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{$endif i386}
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{$ifdef x86_64 }
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REG_PC = REG_RIP;
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REG_FP = REG_RBP;
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REG_SP = REG_RSP;
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REG_PS = REG_RFL;
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REG_R0 = REG_RAX;
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REG_R1 = REG_RDX;
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{$else /* __i386 */ }
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REG_PC = REG_EIP;
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REG_FP = REG_EBP;
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REG_SP = REG_UESP;
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REG_PS = REG_EFL;
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REG_R0 = REG_EAX;
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REG_R1 = REG_EDX;
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{$endif }
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type
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PSigContext = ^TSigContext;
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TSigContext = record
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{ WARNING: this is a blind copy of
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the linux strcuture, probably totally wrong PM }
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gs, __gsh: word;
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fs, __fsh: word;
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es, __esh: word;
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ds, __dsh: word;
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edi: cardinal;
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esi: cardinal;
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ebp: cardinal;
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esp: cardinal;
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ebx: cardinal;
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edx: cardinal;
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ecx: cardinal;
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eax: cardinal;
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trapno: cardinal;
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err: cardinal;
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eip: cardinal;
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cs, __csh: word;
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eflags: cardinal;
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esp_at_signal: cardinal;
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ss, __ssh: word;
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// commented out for now : fpstate: pfpstate;
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oldmask: cardinal;
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cr2: cardinal;
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{$ifdef x86_64}
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TGReg = cint64;
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{$else}
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TGReg = cint32;
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{$endif}
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TGReg32 = cint32;
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TGReg64 = cint64;
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TGRegSet = array[0.._NGREG-1] of TGReg;
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TGRegSet32 = array[0.._NGREG32-1] of TGReg32;
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TGRegSet64 = array[0.._NGREG64-1] of TGReg64;
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type
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FPU_SAVE_TYPE = (fnsave_type, fxsave_type);
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TFPURegs = record
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case longint of
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0: ( fpuregs: array[0..31] of cardinal);
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1: ( fpudregs: array[0..15] of double);
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end;
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PFQ = ^TFQ;
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TFQ = record
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fpq_addr : ^cuint;
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fpq_instr : cuint;
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end;
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(* struct fpchip_state {
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uint32_t state[27]; /* 287/387 saved state */
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uint32_t status; /* saved at exception */
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uint32_t mxcsr; /* SSE control and status */
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uint32_t xstatus; /* SSE mxcsr at exception */
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uint32_t __pad[2]; /* align to 128-bits */
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upad128_t xmm[8]; /* %xmm0-%xmm7 */
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} fpchip_state;
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*)
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TUpad128 = record
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case longint of
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0: (_q : extended;);
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1: (_l : array [0..4-1] of cuint32;);
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end;
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TFPChip_State = record
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state : array [0..27-1] of cuint32;
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status : cuint32;
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mxcsr : cuint32;
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xstatus : cuint32;
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__pad : array [0..1] of cuint32;
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xmm : array [0..8-1] of TUpad128;
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end;
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TFP_emul_space = record
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fp_emul : array [0..248-1] of cuint8;
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fp_epad : array [0..1] of cuint8;
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end;
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TFPU = record
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case longint of
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0: (fpchip_state : TFPChip_state;);
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1: (fp_emul_space : TFP_emul_space;);
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2: (f_fpregs : Array[0..130-1] of cuint32;);
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end;
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TFPRegSet = TFPU;
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TMContext = record
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gregs : TGRegSet;
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fpregs : TFPRegSet;
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end;
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TStack = record
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ss_sp : pointer;
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ss_size : size_t;
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ss_flags : cint;
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end;
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PSigContext = ^TSigContext;
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TSigContext = record
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uc_flags : cuint;
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uc_link : PSigContext;
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uc_sigmask : sigset_t;
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uc_stack : TStack;
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uc_mcontext : TMContext;
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__uc_filler : array[0..5-1] of clong;
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end;
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