mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-09 10:48:30 +02:00
+ factored out TX86AsmOptimizer.PrePeepholeOptIMUL, used now by x86-64 and i386
* generalized and simplified the code git-svn-id: trunk@40162 -
This commit is contained in:
florian
parent
47c9bca7f2
commit
59d5d6ec95
@ -31,6 +31,7 @@ unit aoptutils;
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function MatchOpType(const p : taicpu;type0: toptype) : Boolean;
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function MatchOpType(const p : taicpu;type0,type1 : toptype) : Boolean;
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function MatchOpType(const p : taicpu; type0,type1,type2 : toptype) : Boolean;
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{ skips all labels and returns the next "real" instruction }
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function SkipLabels(hp: tai; var hp2: tai): boolean;
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@ -49,6 +50,12 @@ unit aoptutils;
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end;
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function MatchOpType(const p : taicpu; type0,type1,type2 : toptype) : Boolean;
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begin
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Result:=(p.ops=3) and (p.oper[0]^.typ=type0) and (p.oper[1]^.typ=type1) and (p.oper[2]^.typ=type1);
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end;
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{ skips all labels and returns the next "real" instruction }
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function SkipLabels(hp: tai; var hp2: tai): boolean;
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begin
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@ -169,205 +169,8 @@ begin
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end;
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case taicpu(p).opcode Of
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A_IMUL:
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{changes certain "imul const, %reg"'s to lea sequences}
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begin
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if (taicpu(p).oper[0]^.typ = Top_Const) and
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(taicpu(p).oper[1]^.typ = Top_Reg) and
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(taicpu(p).opsize = S_L) then
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if (taicpu(p).oper[0]^.val = 1) then
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if (taicpu(p).ops = 2) then
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{remove "imul $1, reg"}
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begin
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hp1 := tai(p.Next);
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asml.remove(p);
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p.free;
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p := hp1;
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continue;
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end
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else
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{change "imul $1, reg1, reg2" to "mov reg1, reg2"}
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begin
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hp1 := taicpu.Op_Reg_Reg(A_MOV, S_L, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end
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else if
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((taicpu(p).ops <= 2) or
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(taicpu(p).oper[2]^.typ = Top_Reg)) and
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(taicpu(p).oper[0]^.val <= 12) and
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not(cs_opt_size in current_settings.optimizerswitches) and
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(not(GetNextInstruction(p, hp1)) or
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{GetNextInstruction(p, hp1) and}
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not((tai(hp1).typ = ait_instruction) and
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((taicpu(hp1).opcode=A_Jcc) and
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(taicpu(hp1).condition in [C_O,C_NO])))) then
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begin
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reference_reset(tmpref,1,[]);
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case taicpu(p).oper[0]^.val Of
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3: begin
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{imul 3, reg1, reg2 to
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lea (reg1,reg1,2), reg2
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imul 3, reg1 to
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lea (reg1,reg1,2), reg1}
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 2;
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if (taicpu(p).ops = 2) then
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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5: begin
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{imul 5, reg1, reg2 to
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lea (reg1,reg1,4), reg2
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imul 5, reg1 to
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lea (reg1,reg1,4), reg1}
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 4;
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if (taicpu(p).ops = 2) then
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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6: begin
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{imul 6, reg1, reg2 to
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lea (,reg1,2), reg2
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lea (reg2,reg1,4), reg2
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imul 6, reg1 to
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lea (reg1,reg1,2), reg1
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add reg1, reg1}
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if (current_settings.optimizecputype <= cpu_386) then
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begin
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TmpRef.index := taicpu(p).oper[1]^.reg;
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if (taicpu(p).ops = 3) then
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begin
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TmpRef.base := taicpu(p).oper[2]^.reg;
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TmpRef.ScaleFactor := 4;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
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end
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else
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begin
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hp1 := taicpu.op_reg_reg(A_ADD, S_L,
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taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
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end;
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InsertLLItem(p, p.next, hp1);
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 2;
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if (taicpu(p).ops = 3) then
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begin
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TmpRef.base := NR_NO;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
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taicpu(p).oper[2]^.reg);
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end
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else
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begin
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TmpRef.base := taicpu(p).oper[1]^.reg;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
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end;
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := tai(hp1.next);
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end
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end;
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9: begin
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{imul 9, reg1, reg2 to
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lea (reg1,reg1,8), reg2
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imul 9, reg1 to
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lea (reg1,reg1,8), reg1}
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 8;
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if (taicpu(p).ops = 2) then
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := hp1;
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end;
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10: begin
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{imul 10, reg1, reg2 to
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lea (reg1,reg1,4), reg2
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add reg2, reg2
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imul 10, reg1 to
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lea (reg1,reg1,4), reg1
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add reg1, reg1}
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if (current_settings.optimizecputype <= cpu_386) then
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begin
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if (taicpu(p).ops = 3) then
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hp1 := taicpu.op_reg_reg(A_ADD, S_L,
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taicpu(p).oper[2]^.reg,taicpu(p).oper[2]^.reg)
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else
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hp1 := taicpu.op_reg_reg(A_ADD, S_L,
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taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
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InsertLLItem(p, p.next, hp1);
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.index := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 4;
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if (taicpu(p).ops = 3) then
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg)
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else
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := tai(hp1.next);
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end
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end;
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12: begin
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{imul 12, reg1, reg2 to
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lea (,reg1,4), reg2
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lea (reg2,reg1,8), reg2
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imul 12, reg1 to
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lea (reg1,reg1,2), reg1
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lea (,reg1,4), reg1}
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if (current_settings.optimizecputype <= cpu_386)
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then
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begin
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TmpRef.index := taicpu(p).oper[1]^.reg;
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if (taicpu(p).ops = 3) then
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begin
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TmpRef.base := taicpu(p).oper[2]^.reg;
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TmpRef.ScaleFactor := 8;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
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end
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else
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begin
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TmpRef.base := NR_NO;
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TmpRef.ScaleFactor := 4;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
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end;
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InsertLLItem(p, p.next, hp1);
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reference_reset(tmpref,2,[]);
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TmpRef.index := taicpu(p).oper[1]^.reg;
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if (taicpu(p).ops = 3) then
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begin
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TmpRef.base := NR_NO;
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TmpRef.ScaleFactor := 4;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
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end
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else
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begin
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.ScaleFactor := 2;
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hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
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end;
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p := tai(hp1.next);
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end
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end
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end;
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end;
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end;
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if PrePeepholeOptIMUL(p) then
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Continue;
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A_SAR,A_SHR:
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if PrePeepholeOptSxx(p) then
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continue;
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@ -57,6 +57,7 @@ unit aoptx86;
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function DoSubAddOpt(var p : tai) : Boolean;
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function PrePeepholeOptSxx(var p : tai) : boolean;
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function PrePeepholeOptIMUL(var p : tai) : boolean;
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function OptPass1AND(var p : tai) : boolean;
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function OptPass1VMOVAP(var p : tai) : boolean;
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@ -718,6 +719,91 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.PrePeepholeOptIMUL(var p : tai) : boolean;
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var
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opsize : topsize;
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hp1 : tai;
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tmpref : treference;
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hp2 : taicpu;
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ShiftValue : Cardinal;
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BaseValue : TCGInt;
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begin
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result:=false;
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opsize:=taicpu(p).opsize;
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{ changes certain "imul const, %reg"'s to lea sequences }
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if (MatchOpType(taicpu(p),top_const,top_reg) or
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MatchOpType(taicpu(p),top_const,top_reg,top_reg)) and
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(opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) then
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if (taicpu(p).oper[0]^.val = 1) then
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if (taicpu(p).ops = 2) then
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{ remove "imul $1, reg" }
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begin
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hp1 := tai(p.Next);
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asml.remove(p);
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DebugMsg(SPeepholeOptimization + 'Imul2Nop done',p);
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p.free;
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p := hp1;
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result:=true;
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end
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else
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{ change "imul $1, reg1, reg2" to "mov reg1, reg2" }
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begin
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hp1 := taicpu.Op_Reg_Reg(A_MOV, opsize, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
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InsertLLItem(p.previous, p.next, hp1);
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DebugMsg(SPeepholeOptimization + 'Imul2Mov done',p);
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p.free;
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p := hp1;
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end
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else if
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((taicpu(p).ops <= 2) or
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(taicpu(p).oper[2]^.typ = Top_Reg)) and
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not(cs_opt_size in current_settings.optimizerswitches) and
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(not(GetNextInstruction(p, hp1)) or
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not((tai(hp1).typ = ait_instruction) and
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((taicpu(hp1).opcode=A_Jcc) and
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(taicpu(hp1).condition in [C_O,C_NO])))) then
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begin
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{
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imul X, reg1, reg2 to
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lea (reg1,reg1,Y), reg2
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shl ZZ,reg2
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imul XX, reg1 to
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lea (reg1,reg1,YY), reg1
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shl ZZ,reg2
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This optimziation makes sense for pretty much every x86, except the VIA Nano3000: it has IMUL latency 2, lea/shl pair as well,
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it does not exist as a separate optimization target in FPC though.
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This optimziation can be applied as long as only two bits are set in the constant and those two bits are separated by
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at most two zeros
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}
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reference_reset(tmpref,1,[]);
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if (PopCnt(QWord(taicpu(p).oper[0]^.val))=2) and (BsrQWord(taicpu(p).oper[0]^.val)-BsfQWord(taicpu(p).oper[0]^.val)<=3) then
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begin
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ShiftValue:=BsfQWord(taicpu(p).oper[0]^.val);
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BaseValue:=taicpu(p).oper[0]^.val shr ShiftValue;
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TmpRef.base := taicpu(p).oper[1]^.reg;
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TmpRef.index := taicpu(p).oper[1]^.reg;
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if not(BaseValue in [3,5,9]) then
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Internalerror(2018110101);
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TmpRef.ScaleFactor := BaseValue-1;
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if (taicpu(p).ops = 2) then
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hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[1]^.reg)
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else
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hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[2]^.reg);
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AsmL.InsertAfter(hp1,p);
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DebugMsg(SPeepholeOptimization + 'Imul2LeaShl done',p);
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AsmL.Remove(p);
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taicpu(hp1).fileinfo:=taicpu(p).fileinfo;
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p.free;
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p := hp1;
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if ShiftValue>0 then
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AsmL.InsertAfter(taicpu.op_const_reg(A_SHL, opsize, ShiftValue, taicpu(hp1).oper[1]^.reg),hp1);
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end;
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end;
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end;
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function TX86AsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
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var
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p: taicpu;
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@ -51,6 +51,8 @@ uses
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_IMUL:
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result:=PrePeepholeOptIMUL(p);
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A_SAR,A_SHR:
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result:=PrePeepholeOptSxx(p);
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end;
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