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* improvements and fixes in tcg8086.a_load_reg_reg and .a_load_ref_reg:

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o When expanding from a OS_8 to a 16-bit or 32-bit tcgsize, use the R_SUBH
    subregister to initialize the high 16 bits of the register to zero. This
    generates shorter and faster code, without increasing register
    interferences, because R_SUBH has the same register constraints on i8086 as
    R_SUBL, which is already used on the same imaginary register.
  o After performing operations on the 8-bit subparts of a register that was
    initially 16-bit, call makeregsize(OS_16) to notify the register allocator
    that the register is once again 16-bit.

git-svn-id: trunk@26328 -
This commit is contained in:
nickysn 2013-12-30 21:20:10 +00:00
parent bf59a848b4
commit 5d0814016d
1 changed files with 8 additions and 2 deletions
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10
compiler/i8086/cgcpu.pas
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@ -1154,9 +1154,11 @@ unit cgcpu;
case fromsize of
OS_8:
begin
list.concat(taicpu.op_const_reg(A_MOV, S_W, 0, reg));
reg := makeregsize(list, reg, OS_8);
list.concat(taicpu.op_ref_reg(A_MOV, S_B, tmpref, reg));
setsubreg(reg, R_SUBH);
list.concat(taicpu.op_const_reg(A_MOV, S_B, 0, reg));
makeregsize(list, reg, OS_16);
end;
OS_S8:
begin
@ -1176,9 +1178,11 @@ unit cgcpu;
OS_8:
begin
list.concat(taicpu.op_const_reg(A_MOV,S_W,0,GetNextReg(reg)));
list.concat(taicpu.op_const_reg(A_MOV, S_W, 0, reg));
reg := makeregsize(list, reg, OS_8);
list.concat(taicpu.op_ref_reg(A_MOV, S_B, tmpref, reg));
setsubreg(reg, R_SUBH);
list.concat(taicpu.op_const_reg(A_MOV, S_B, 0, reg));
makeregsize(list, reg, OS_16);
end;
OS_S8:
begin
@ -1266,6 +1270,7 @@ unit cgcpu;
add_mov(taicpu.op_reg_reg(A_MOV, S_B, reg1, reg2));
setsubreg(reg2,R_SUBH);
list.concat(taicpu.op_const_reg(A_MOV, S_B, 0, reg2));
makeregsize(list, reg2, OS_16);
end;
OS_S8:
begin
@ -1293,6 +1298,7 @@ unit cgcpu;
add_mov(taicpu.op_reg_reg(A_MOV, S_B, reg1, reg2));
setsubreg(reg2,R_SUBH);
list.concat(taicpu.op_const_reg(A_MOV, S_B, 0, reg2));
makeregsize(list, reg2, OS_16);
end;
OS_S8:
begin