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+ implemented a_load_const_ref for more efficient Z80 code generation for const assignment to local variables

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git-svn-id: branches/z80@44528 -
This commit is contained in:
nickysn 2020-04-03 02:23:05 +00:00
parent 4fe04ac53a
commit 5ddd0dd9b8
2 changed files with 48 additions and 0 deletions
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12
compiler/z80/aasmcpu.pas
View File

@ -51,6 +51,8 @@ uses
pinsentry=^tinsentry;
{ taicpu }
taicpu = class(tai_cpu_abstract_sym)
constructor op_none(op : tasmop);
@ -63,6 +65,7 @@ uses
constructor op_reg_const(op:tasmop; _op1: tregister; _op2: LongInt);
constructor op_const_reg(op:tasmop; _op1: LongInt; _op2: tregister);
constructor op_ref_reg(op : tasmop;const _op1 : treference;_op2 : tregister);
constructor op_ref_const(op:tasmop; _op1: treference; _op2: LongInt);
{ this is for Jmp instructions }
constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
@ -179,6 +182,15 @@ implementation
end;
constructor taicpu.op_ref_const(op: tasmop; _op1: treference; _op2: LongInt);
begin
inherited create(op);
ops:=2;
loadref(0,_op1);
loadconst(1,aint(_op2));
end;
constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
begin
inherited create(op);

36
compiler/z80/cgcpu.pas
View File

@ -59,6 +59,7 @@ unit cgcpu;
{ move instructions }
procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
procedure a_load_const_ref(list : TAsmList;size : tcgsize;a : tcgint;const ref : treference);override;
procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
@ -849,6 +850,41 @@ unit cgcpu;
end;
procedure tcgz80.a_load_const_ref(list: TAsmList; size: tcgsize; a: tcgint; const ref: treference);
var
mask : qword;
shift : byte;
href: treference;
i: Integer;
begin
mask:=$ff;
shift:=0;
href:=ref;
if (href.base=NR_NO) and (href.index<>NR_NO) then
begin
href.base:=href.index;
href.index:=NR_NO;
end;
if not assigned(href.symbol) and
((href.base=NR_IX) or (href.base=NR_IY) or
((href.base=NR_HL) and (size in [OS_8,OS_S8]) and (href.offset=0))) then
begin
for i:=tcgsize2size[size] downto 1 do
begin
list.Concat(taicpu.op_ref_const(A_LD,href,(qword(a) and mask) shr shift));
if i<>1 then
begin
mask:=mask shl 8;
inc(shift,8);
inc(href.offset);
end;
end;
end
else
inherited;
end;
procedure tcgz80.maybegetcpuregister(list:tasmlist;reg : tregister);
begin
{ allocate the register only, if a cpu register is passed }