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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-09-12 10:09:08 +02:00
Rename fields of tspillregsinfo record to avoid having same field names as treginfo record
This commit is contained in:
Pierre Muller
parent
cbe5fabd3d
commit
5e6e24ec08
@ -41,8 +41,8 @@ unit rgllvm;
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procedure do_spill_read(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
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procedure do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
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protected
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function instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; override;
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procedure substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); override;
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function instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; override;
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procedure substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); override;
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procedure determine_spill_registers(list: TasmList; headertai: tai); override;
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procedure get_spill_temp(list:TAsmlist;spill_temps: Pspill_temp_list; supreg: tsuperregister);override;
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strict protected
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@ -121,7 +121,7 @@ implementation
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end;
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function trgllvm.instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
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function trgllvm.instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
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var
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paracnt: longint;
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callpara: pllvmcallpara;
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@ -138,7 +138,7 @@ implementation
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if (callpara^.val.typ=top_reg) and
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(getregtype(callpara^.val.register)=regtype) then
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begin
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result:=addreginfo(regs,r,callpara^.val.register,operand_read) or result;
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result:=addreginfo(spregs,r,callpara^.val.register,operand_read) or result;
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break
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end;
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end;
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@ -150,7 +150,7 @@ implementation
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end;
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procedure trgllvm.substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
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procedure trgllvm.substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
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var
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i, paracnt: longint;
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callpara: pllvmcallpara;
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@ -164,7 +164,7 @@ implementation
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callpara:=pllvmcallpara(paras[paracnt]);
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if (callpara^.val.typ=top_reg) and
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(getregtype(callpara^.val.register)=regtype) then
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try_replace_reg(regs, callpara^.val.register,true);
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try_replace_reg(spregs, callpara^.val.register,true);
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end;
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end;
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else
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@ -134,8 +134,8 @@ unit rgobj;
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regread, regwritten, mustbespilled: boolean;
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end;
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tspillregsinfo = record
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reginfocount: longint;
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reginfo: array[0..3] of tspillreginfo;
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spillreginfocount: longint;
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spillreginfo: array[0..3] of tspillreginfo;
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end;
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Pspill_temp_list=^Tspill_temp_list;
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@ -216,10 +216,10 @@ unit rgobj;
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual;
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function addreginfo(var regs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
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function instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; virtual;
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procedure substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); virtual;
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procedure try_replace_reg(const regs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
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function addreginfo(var spregs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
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function instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; virtual;
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procedure substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); virtual;
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procedure try_replace_reg(const spregs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
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function instr_spill_register(list:TAsmList;
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instr:tai_cpu_abstract_sym;
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const r:Tsuperregisterset;
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@ -2624,47 +2624,47 @@ unit rgobj;
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end;
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function trgobj.addreginfo(var regs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
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function trgobj.addreginfo(var spregs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
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var
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i, tmpindex: longint;
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supreg: tsuperregister;
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begin
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result:=false;
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tmpindex := regs.reginfocount;
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tmpindex := spregs.spillreginfocount;
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supreg := get_alias(getsupreg(reg));
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{ did we already encounter this register? }
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for i := 0 to pred(regs.reginfocount) do
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if (regs.reginfo[i].orgreg = supreg) then
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for i := 0 to pred(spregs.spillreginfocount) do
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if (spregs.spillreginfo[i].orgreg = supreg) then
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begin
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tmpindex := i;
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break;
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end;
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if tmpindex > high(regs.reginfo) then
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if tmpindex > high(spregs.spillreginfo) then
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internalerror(2003120301);
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regs.reginfo[tmpindex].orgreg := supreg;
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include(regs.reginfo[tmpindex].spillregconstraints,get_spill_subreg(reg));
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spregs.spillreginfo[tmpindex].orgreg := supreg;
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include(spregs.spillreginfo[tmpindex].spillregconstraints,get_spill_subreg(reg));
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if supregset_in(r,supreg) then
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begin
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{ add/update info on this register }
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regs.reginfo[tmpindex].mustbespilled := true;
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spregs.spillreginfo[tmpindex].mustbespilled := true;
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case operation of
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operand_read:
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regs.reginfo[tmpindex].regread := true;
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spregs.spillreginfo[tmpindex].regread := true;
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operand_write:
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regs.reginfo[tmpindex].regwritten := true;
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spregs.spillreginfo[tmpindex].regwritten := true;
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operand_readwrite:
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begin
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regs.reginfo[tmpindex].regread := true;
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regs.reginfo[tmpindex].regwritten := true;
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spregs.spillreginfo[tmpindex].regread := true;
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spregs.spillreginfo[tmpindex].regwritten := true;
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end;
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end;
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result:=true;
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end;
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inc(regs.reginfocount,ord(regs.reginfocount=tmpindex));
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inc(spregs.spillreginfocount,ord(spregs.spillreginfocount=tmpindex));
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end;
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function trgobj.instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
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function trgobj.instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
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begin
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result:=false;
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with instr.oper[opidx]^ do
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@ -2673,7 +2673,7 @@ unit rgobj;
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top_reg:
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begin
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if (getregtype(reg) = regtype) then
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result:=addreginfo(regs,r,reg,instr.spilling_get_operation_type(opidx));
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result:=addreginfo(spregs,r,reg,instr.spilling_get_operation_type(opidx));
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end;
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top_ref:
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begin
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@ -2682,14 +2682,14 @@ unit rgobj;
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begin
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if (base <> NR_NO) and
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(getregtype(base)=regtype) then
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result:=addreginfo(regs,r,base,instr.spilling_get_operation_type_ref(opidx,base));
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result:=addreginfo(spregs,r,base,instr.spilling_get_operation_type_ref(opidx,base));
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if (index <> NR_NO) and
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(getregtype(index)=regtype) then
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result:=addreginfo(regs,r,index,instr.spilling_get_operation_type_ref(opidx,index)) or result;
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result:=addreginfo(spregs,r,index,instr.spilling_get_operation_type_ref(opidx,index)) or result;
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{$if defined(x86)}
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if (segment <> NR_NO) and
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(getregtype(segment)=regtype) then
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result:=addreginfo(regs,r,segment,instr.spilling_get_operation_type_ref(opidx,segment)) or result;
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result:=addreginfo(spregs,r,segment,instr.spilling_get_operation_type_ref(opidx,segment)) or result;
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{$endif defined(x86)}
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end;
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end;
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@ -2698,7 +2698,7 @@ unit rgobj;
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begin
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if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then
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if shifterop^.rs<>NR_NO then
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result:=addreginfo(regs,r,shifterop^.rs,operand_read);
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result:=addreginfo(spregs,r,shifterop^.rs,operand_read);
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end;
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{$endif ARM}
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else
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@ -2708,34 +2708,34 @@ unit rgobj;
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end;
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procedure trgobj.try_replace_reg(const regs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
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procedure trgobj.try_replace_reg(const spregs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
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var
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i: longint;
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supreg: tsuperregister;
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begin
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supreg:=get_alias(getsupreg(reg));
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for i:=0 to pred(regs.reginfocount) do
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if (regs.reginfo[i].mustbespilled) and
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(regs.reginfo[i].orgreg=supreg) then
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for i:=0 to pred(spregs.spillreginfocount) do
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if (spregs.spillreginfo[i].mustbespilled) and
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(spregs.spillreginfo[i].orgreg=supreg) then
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begin
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{ Only replace supreg }
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if useloadreg then
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setsupreg(reg, getsupreg(regs.reginfo[i].loadreg))
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setsupreg(reg, getsupreg(spregs.spillreginfo[i].loadreg))
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else
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setsupreg(reg, getsupreg(regs.reginfo[i].storereg));
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setsupreg(reg, getsupreg(spregs.spillreginfo[i].storereg));
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break;
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end;
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end;
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procedure trgobj.substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
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procedure trgobj.substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
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begin
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with instr.oper[opidx]^ do
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case typ of
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top_reg:
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begin
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if (getregtype(reg) = regtype) then
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try_replace_reg(regs, reg, not ssa_safe or
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try_replace_reg(spregs, reg, not ssa_safe or
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(instr.spilling_get_operation_type(opidx)=operand_read));
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end;
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top_ref:
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@ -2744,16 +2744,16 @@ unit rgobj;
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begin
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if (ref^.base <> NR_NO) and
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(getregtype(ref^.base)=regtype) then
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try_replace_reg(regs, ref^.base,
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try_replace_reg(spregs, ref^.base,
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not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.base)=operand_read));
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if (ref^.index <> NR_NO) and
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(getregtype(ref^.index)=regtype) then
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try_replace_reg(regs, ref^.index,
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try_replace_reg(spregs, ref^.index,
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not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.index)=operand_read));
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{$if defined(x86)}
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if (ref^.segment <> NR_NO) and
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(getregtype(ref^.segment)=regtype) then
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try_replace_reg(regs, ref^.segment, true { always read-only });
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try_replace_reg(spregs, ref^.segment, true { always read-only });
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{$endif defined(x86)}
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end;
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end;
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@ -2761,7 +2761,7 @@ unit rgobj;
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top_shifterop:
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begin
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if regtype in [R_INTREGISTER, R_ADDRESSREGISTER] then
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try_replace_reg(regs, shifterop^.rs, true { always read-only });
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try_replace_reg(spregs, shifterop^.rs, true { always read-only });
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end;
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{$endif ARM}
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else
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@ -2776,7 +2776,7 @@ unit rgobj;
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const spilltemplist:Tspill_temp_list): boolean;
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var
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counter: longint;
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regs: tspillregsinfo;
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spregs: tspillregsinfo;
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spilled: boolean;
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var
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loadpos,
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@ -2784,32 +2784,32 @@ unit rgobj;
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oldlive_registers : tsuperregisterworklist;
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begin
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result := false;
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fillchar(regs,sizeof(regs),0);
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for counter := low(regs.reginfo) to high(regs.reginfo) do
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fillchar(spregs,sizeof(spregs),0);
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for counter := low(spregs.spillreginfo) to high(spregs.spillreginfo) do
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begin
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regs.reginfo[counter].orgreg := RS_INVALID;
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regs.reginfo[counter].loadreg := NR_INVALID;
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regs.reginfo[counter].storereg := NR_INVALID;
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spregs.spillreginfo[counter].orgreg := RS_INVALID;
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spregs.spillreginfo[counter].loadreg := NR_INVALID;
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spregs.spillreginfo[counter].storereg := NR_INVALID;
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end;
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spilled := false;
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{ check whether and if so which and how (read/written) this instructions contains
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registers that must be spilled }
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for counter := 0 to instr.ops-1 do
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spilled:=instr_get_oper_spilling_info(regs,r,instr,counter) or spilled;
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spilled:=instr_get_oper_spilling_info(spregs,r,instr,counter) or spilled;
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{ if no spilling for this instruction we can leave }
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if not spilled then
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exit;
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{ Check if the instruction is "OP reg1,reg2" and reg1 is coalesced with reg2 }
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if (regs.reginfocount=1) and (instr.ops=2) and
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if (spregs.spillreginfocount=1) and (instr.ops=2) and
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(instr.oper[0]^.typ=top_reg) and (instr.oper[1]^.typ=top_reg) and
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(getregtype(instr.oper[0]^.reg)=getregtype(instr.oper[1]^.reg)) then
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begin
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{ Set both registers in the instruction to the same register }
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setsupreg(instr.oper[0]^.reg, regs.reginfo[0].orgreg);
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setsupreg(instr.oper[1]^.reg, regs.reginfo[0].orgreg);
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setsupreg(instr.oper[0]^.reg, spregs.spillreginfo[0].orgreg);
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setsupreg(instr.oper[1]^.reg, spregs.spillreginfo[0].orgreg);
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{ In case of MOV reg,reg no spilling is needed.
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This MOV will be removed later in translate_registers() }
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if instr.is_same_reg_move(regtype) then
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@ -2822,8 +2822,8 @@ unit rgobj;
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For non-x86 it is nevertheless possible to replace moves to/from the register
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with loads/stores to spilltemp (Sergei) }
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for counter := 0 to pred(regs.reginfocount) do
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with regs.reginfo[counter] do
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for counter := 0 to pred(spregs.spillreginfocount) do
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with spregs.spillreginfo[counter] do
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begin
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if mustbespilled then
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begin
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@ -2891,12 +2891,12 @@ unit rgobj;
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loadpos:=tai(loadpos.next);
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{ Load the spilled registers }
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for counter := 0 to pred(regs.reginfocount) do
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with regs.reginfo[counter] do
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for counter := 0 to pred(spregs.spillreginfocount) do
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with spregs.spillreginfo[counter] do
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begin
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if mustbespilled and regread then
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begin
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loadreg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints);
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loadreg:=getregisterinline(list,spregs.spillreginfo[counter].spillregconstraints);
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do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],loadreg,orgreg);
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include(reginfo[getsupreg(loadreg)].flags,ri_spill_helper);
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end;
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@ -2904,8 +2904,8 @@ unit rgobj;
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{ Release temp registers of read-only registers, and add reference of the instruction
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to the reginfo }
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for counter := 0 to pred(regs.reginfocount) do
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with regs.reginfo[counter] do
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for counter := 0 to pred(spregs.spillreginfocount) do
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with spregs.spillreginfo[counter] do
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begin
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if mustbespilled and regread and
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(ssa_safe or
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@ -2926,8 +2926,8 @@ unit rgobj;
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{ Allocate temp registers of write-only registers, and add reference of the instruction
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to the reginfo }
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for counter := 0 to pred(regs.reginfocount) do
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with regs.reginfo[counter] do
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for counter := 0 to pred(spregs.spillreginfocount) do
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with spregs.spillreginfo[counter] do
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begin
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if mustbespilled and regwritten then
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begin
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@ -2935,7 +2935,7 @@ unit rgobj;
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if (not regread) or
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ssa_safe then
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begin
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storereg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints);
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storereg:=getregisterinline(list,spregs.spillreginfo[counter].spillregconstraints);
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include(reginfo[getsupreg(storereg)].flags,ri_spill_helper);
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{ we also use loadreg for store replacements in case we
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don't have ensure ssa -> initialise loadreg even if
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@ -2962,8 +2962,8 @@ unit rgobj;
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if not assigned(instr.next) then
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list.concat(tai_marker.Create(mark_Position));
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storepos:=tai(instr.next);
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for counter := 0 to pred(regs.reginfocount) do
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with regs.reginfo[counter] do
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for counter := 0 to pred(spregs.spillreginfocount) do
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with spregs.spillreginfo[counter] do
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begin
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if mustbespilled and regwritten then
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begin
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@ -2980,7 +2980,7 @@ unit rgobj;
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{ substitute registers }
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for counter:=0 to instr.ops-1 do
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substitute_spilled_registers(regs,instr,counter);
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substitute_spilled_registers(spregs,instr,counter);
|
||||
{ We have modified the instruction; perhaps the new instruction has
|
||||
certain constraints regarding which imaginary registers interfere
|
||||
with certain physical registers. }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user