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Rename fields of tspillregsinfo record to avoid having same field names as treginfo record

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This commit is contained in:
Pierre Muller 2023-09-22 23:06:46 +02:00
parent cbe5fabd3d
commit 5e6e24ec08
2 changed files with 66 additions and 66 deletions
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12
compiler/llvm/rgllvm.pas
View File

@ -41,8 +41,8 @@ unit rgllvm;
procedure do_spill_read(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override; procedure do_spill_read(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
procedure do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override; procedure do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister; orgsupreg: tsuperregister); override;
protected protected
function instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; override; function instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; override;
procedure substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); override; procedure substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); override;
procedure determine_spill_registers(list: TasmList; headertai: tai); override; procedure determine_spill_registers(list: TasmList; headertai: tai); override;
procedure get_spill_temp(list:TAsmlist;spill_temps: Pspill_temp_list; supreg: tsuperregister);override; procedure get_spill_temp(list:TAsmlist;spill_temps: Pspill_temp_list; supreg: tsuperregister);override;
strict protected strict protected
@ -121,7 +121,7 @@ implementation
end; end;
function trgllvm.instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; function trgllvm.instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
var var
paracnt: longint; paracnt: longint;
callpara: pllvmcallpara; callpara: pllvmcallpara;
@ -138,7 +138,7 @@ implementation
if (callpara^.val.typ=top_reg) and if (callpara^.val.typ=top_reg) and
(getregtype(callpara^.val.register)=regtype) then (getregtype(callpara^.val.register)=regtype) then
begin begin
result:=addreginfo(regs,r,callpara^.val.register,operand_read) or result; result:=addreginfo(spregs,r,callpara^.val.register,operand_read) or result;
break break
end; end;
end; end;
@ -150,7 +150,7 @@ implementation
end; end;
procedure trgllvm.substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); procedure trgllvm.substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
var var
i, paracnt: longint; i, paracnt: longint;
callpara: pllvmcallpara; callpara: pllvmcallpara;
@ -164,7 +164,7 @@ implementation
callpara:=pllvmcallpara(paras[paracnt]); callpara:=pllvmcallpara(paras[paracnt]);
if (callpara^.val.typ=top_reg) and if (callpara^.val.typ=top_reg) and
(getregtype(callpara^.val.register)=regtype) then (getregtype(callpara^.val.register)=regtype) then
try_replace_reg(regs, callpara^.val.register,true); try_replace_reg(spregs, callpara^.val.register,true);
end; end;
end; end;
else else

120
compiler/rgobj.pas
View File

@ -134,8 +134,8 @@ unit rgobj;
regread, regwritten, mustbespilled: boolean; regread, regwritten, mustbespilled: boolean;
end; end;
tspillregsinfo = record tspillregsinfo = record
reginfocount: longint; spillreginfocount: longint;
reginfo: array[0..3] of tspillreginfo; spillreginfo: array[0..3] of tspillreginfo;
end; end;
Pspill_temp_list=^Tspill_temp_list; Pspill_temp_list=^Tspill_temp_list;
@ -216,10 +216,10 @@ unit rgobj;
procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual; procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual;
procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual; procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister;orgsupreg:tsuperregister);virtual;
function addreginfo(var regs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean; function addreginfo(var spregs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
function instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; virtual; function instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; virtual;
procedure substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); virtual; procedure substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); virtual;
procedure try_replace_reg(const regs: tspillregsinfo; var reg: tregister; useloadreg: boolean); procedure try_replace_reg(const spregs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
function instr_spill_register(list:TAsmList; function instr_spill_register(list:TAsmList;
instr:tai_cpu_abstract_sym; instr:tai_cpu_abstract_sym;
const r:Tsuperregisterset; const r:Tsuperregisterset;
@ -2624,47 +2624,47 @@ unit rgobj;
end; end;
function trgobj.addreginfo(var regs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean; function trgobj.addreginfo(var spregs: tspillregsinfo; const r: tsuperregisterset; reg: tregister; operation: topertype): boolean;
var var
i, tmpindex: longint; i, tmpindex: longint;
supreg: tsuperregister; supreg: tsuperregister;
begin begin
result:=false; result:=false;
tmpindex := regs.reginfocount; tmpindex := spregs.spillreginfocount;
supreg := get_alias(getsupreg(reg)); supreg := get_alias(getsupreg(reg));
{ did we already encounter this register? } { did we already encounter this register? }
for i := 0 to pred(regs.reginfocount) do for i := 0 to pred(spregs.spillreginfocount) do
if (regs.reginfo[i].orgreg = supreg) then if (spregs.spillreginfo[i].orgreg = supreg) then
begin begin
tmpindex := i; tmpindex := i;
break; break;
end; end;
if tmpindex > high(regs.reginfo) then if tmpindex > high(spregs.spillreginfo) then
internalerror(2003120301); internalerror(2003120301);
regs.reginfo[tmpindex].orgreg := supreg; spregs.spillreginfo[tmpindex].orgreg := supreg;
include(regs.reginfo[tmpindex].spillregconstraints,get_spill_subreg(reg)); include(spregs.spillreginfo[tmpindex].spillregconstraints,get_spill_subreg(reg));
if supregset_in(r,supreg) then if supregset_in(r,supreg) then
begin begin
{ add/update info on this register } { add/update info on this register }
regs.reginfo[tmpindex].mustbespilled := true; spregs.spillreginfo[tmpindex].mustbespilled := true;
case operation of case operation of
operand_read: operand_read:
regs.reginfo[tmpindex].regread := true; spregs.spillreginfo[tmpindex].regread := true;
operand_write: operand_write:
regs.reginfo[tmpindex].regwritten := true; spregs.spillreginfo[tmpindex].regwritten := true;
operand_readwrite: operand_readwrite:
begin begin
regs.reginfo[tmpindex].regread := true; spregs.spillreginfo[tmpindex].regread := true;
regs.reginfo[tmpindex].regwritten := true; spregs.spillreginfo[tmpindex].regwritten := true;
end; end;
end; end;
result:=true; result:=true;
end; end;
inc(regs.reginfocount,ord(regs.reginfocount=tmpindex)); inc(spregs.spillreginfocount,ord(spregs.spillreginfocount=tmpindex));
end; end;
function trgobj.instr_get_oper_spilling_info(var regs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean; function trgobj.instr_get_oper_spilling_info(var spregs: tspillregsinfo; const r: tsuperregisterset; instr: tai_cpu_abstract_sym; opidx: longint): boolean;
begin begin
result:=false; result:=false;
with instr.oper[opidx]^ do with instr.oper[opidx]^ do
@ -2673,7 +2673,7 @@ unit rgobj;
top_reg: top_reg:
begin begin
if (getregtype(reg) = regtype) then if (getregtype(reg) = regtype) then
result:=addreginfo(regs,r,reg,instr.spilling_get_operation_type(opidx)); result:=addreginfo(spregs,r,reg,instr.spilling_get_operation_type(opidx));
end; end;
top_ref: top_ref:
begin begin
@ -2682,14 +2682,14 @@ unit rgobj;
begin begin
if (base <> NR_NO) and if (base <> NR_NO) and
(getregtype(base)=regtype) then (getregtype(base)=regtype) then
result:=addreginfo(regs,r,base,instr.spilling_get_operation_type_ref(opidx,base)); result:=addreginfo(spregs,r,base,instr.spilling_get_operation_type_ref(opidx,base));
if (index <> NR_NO) and if (index <> NR_NO) and
(getregtype(index)=regtype) then (getregtype(index)=regtype) then
result:=addreginfo(regs,r,index,instr.spilling_get_operation_type_ref(opidx,index)) or result; result:=addreginfo(spregs,r,index,instr.spilling_get_operation_type_ref(opidx,index)) or result;
{$if defined(x86)} {$if defined(x86)}
if (segment <> NR_NO) and if (segment <> NR_NO) and
(getregtype(segment)=regtype) then (getregtype(segment)=regtype) then
result:=addreginfo(regs,r,segment,instr.spilling_get_operation_type_ref(opidx,segment)) or result; result:=addreginfo(spregs,r,segment,instr.spilling_get_operation_type_ref(opidx,segment)) or result;
{$endif defined(x86)} {$endif defined(x86)}
end; end;
end; end;
@ -2698,7 +2698,7 @@ unit rgobj;
begin begin
if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then
if shifterop^.rs<>NR_NO then if shifterop^.rs<>NR_NO then
result:=addreginfo(regs,r,shifterop^.rs,operand_read); result:=addreginfo(spregs,r,shifterop^.rs,operand_read);
end; end;
{$endif ARM} {$endif ARM}
else else
@ -2708,34 +2708,34 @@ unit rgobj;
end; end;
procedure trgobj.try_replace_reg(const regs: tspillregsinfo; var reg: tregister; useloadreg: boolean); procedure trgobj.try_replace_reg(const spregs: tspillregsinfo; var reg: tregister; useloadreg: boolean);
var var
i: longint; i: longint;
supreg: tsuperregister; supreg: tsuperregister;
begin begin
supreg:=get_alias(getsupreg(reg)); supreg:=get_alias(getsupreg(reg));
for i:=0 to pred(regs.reginfocount) do for i:=0 to pred(spregs.spillreginfocount) do
if (regs.reginfo[i].mustbespilled) and if (spregs.spillreginfo[i].mustbespilled) and
(regs.reginfo[i].orgreg=supreg) then (spregs.spillreginfo[i].orgreg=supreg) then
begin begin
{ Only replace supreg } { Only replace supreg }
if useloadreg then if useloadreg then
setsupreg(reg, getsupreg(regs.reginfo[i].loadreg)) setsupreg(reg, getsupreg(spregs.spillreginfo[i].loadreg))
else else
setsupreg(reg, getsupreg(regs.reginfo[i].storereg)); setsupreg(reg, getsupreg(spregs.spillreginfo[i].storereg));
break; break;
end; end;
end; end;
procedure trgobj.substitute_spilled_registers(const regs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint); procedure trgobj.substitute_spilled_registers(const spregs: tspillregsinfo; instr: tai_cpu_abstract_sym; opidx: longint);
begin begin
with instr.oper[opidx]^ do with instr.oper[opidx]^ do
case typ of case typ of
top_reg: top_reg:
begin begin
if (getregtype(reg) = regtype) then if (getregtype(reg) = regtype) then
try_replace_reg(regs, reg, not ssa_safe or try_replace_reg(spregs, reg, not ssa_safe or
(instr.spilling_get_operation_type(opidx)=operand_read)); (instr.spilling_get_operation_type(opidx)=operand_read));
end; end;
top_ref: top_ref:
@ -2744,16 +2744,16 @@ unit rgobj;
begin begin
if (ref^.base <> NR_NO) and if (ref^.base <> NR_NO) and
(getregtype(ref^.base)=regtype) then (getregtype(ref^.base)=regtype) then
try_replace_reg(regs, ref^.base, try_replace_reg(spregs, ref^.base,
not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.base)=operand_read)); not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.base)=operand_read));
if (ref^.index <> NR_NO) and if (ref^.index <> NR_NO) and
(getregtype(ref^.index)=regtype) then (getregtype(ref^.index)=regtype) then
try_replace_reg(regs, ref^.index, try_replace_reg(spregs, ref^.index,
not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.index)=operand_read)); not ssa_safe or (instr.spilling_get_operation_type_ref(opidx, ref^.index)=operand_read));
{$if defined(x86)} {$if defined(x86)}
if (ref^.segment <> NR_NO) and if (ref^.segment <> NR_NO) and
(getregtype(ref^.segment)=regtype) then (getregtype(ref^.segment)=regtype) then
try_replace_reg(regs, ref^.segment, true { always read-only }); try_replace_reg(spregs, ref^.segment, true { always read-only });
{$endif defined(x86)} {$endif defined(x86)}
end; end;
end; end;
@ -2761,7 +2761,7 @@ unit rgobj;
top_shifterop: top_shifterop:
begin begin
if regtype in [R_INTREGISTER, R_ADDRESSREGISTER] then if regtype in [R_INTREGISTER, R_ADDRESSREGISTER] then
try_replace_reg(regs, shifterop^.rs, true { always read-only }); try_replace_reg(spregs, shifterop^.rs, true { always read-only });
end; end;
{$endif ARM} {$endif ARM}
else else
@ -2776,7 +2776,7 @@ unit rgobj;
const spilltemplist:Tspill_temp_list): boolean; const spilltemplist:Tspill_temp_list): boolean;
var var
counter: longint; counter: longint;
regs: tspillregsinfo; spregs: tspillregsinfo;
spilled: boolean; spilled: boolean;
var var
loadpos, loadpos,
@ -2784,32 +2784,32 @@ unit rgobj;
oldlive_registers : tsuperregisterworklist; oldlive_registers : tsuperregisterworklist;
begin begin
result := false; result := false;
fillchar(regs,sizeof(regs),0); fillchar(spregs,sizeof(spregs),0);
for counter := low(regs.reginfo) to high(regs.reginfo) do for counter := low(spregs.spillreginfo) to high(spregs.spillreginfo) do
begin begin
regs.reginfo[counter].orgreg := RS_INVALID; spregs.spillreginfo[counter].orgreg := RS_INVALID;
regs.reginfo[counter].loadreg := NR_INVALID; spregs.spillreginfo[counter].loadreg := NR_INVALID;
regs.reginfo[counter].storereg := NR_INVALID; spregs.spillreginfo[counter].storereg := NR_INVALID;
end; end;
spilled := false; spilled := false;
{ check whether and if so which and how (read/written) this instructions contains { check whether and if so which and how (read/written) this instructions contains
registers that must be spilled } registers that must be spilled }
for counter := 0 to instr.ops-1 do for counter := 0 to instr.ops-1 do
spilled:=instr_get_oper_spilling_info(regs,r,instr,counter) or spilled; spilled:=instr_get_oper_spilling_info(spregs,r,instr,counter) or spilled;
{ if no spilling for this instruction we can leave } { if no spilling for this instruction we can leave }
if not spilled then if not spilled then
exit; exit;
{ Check if the instruction is "OP reg1,reg2" and reg1 is coalesced with reg2 } { Check if the instruction is "OP reg1,reg2" and reg1 is coalesced with reg2 }
if (regs.reginfocount=1) and (instr.ops=2) and if (spregs.spillreginfocount=1) and (instr.ops=2) and
(instr.oper[0]^.typ=top_reg) and (instr.oper[1]^.typ=top_reg) and (instr.oper[0]^.typ=top_reg) and (instr.oper[1]^.typ=top_reg) and
(getregtype(instr.oper[0]^.reg)=getregtype(instr.oper[1]^.reg)) then (getregtype(instr.oper[0]^.reg)=getregtype(instr.oper[1]^.reg)) then
begin begin
{ Set both registers in the instruction to the same register } { Set both registers in the instruction to the same register }
setsupreg(instr.oper[0]^.reg, regs.reginfo[0].orgreg); setsupreg(instr.oper[0]^.reg, spregs.spillreginfo[0].orgreg);
setsupreg(instr.oper[1]^.reg, regs.reginfo[0].orgreg); setsupreg(instr.oper[1]^.reg, spregs.spillreginfo[0].orgreg);
{ In case of MOV reg,reg no spilling is needed. { In case of MOV reg,reg no spilling is needed.
This MOV will be removed later in translate_registers() } This MOV will be removed later in translate_registers() }
if instr.is_same_reg_move(regtype) then if instr.is_same_reg_move(regtype) then
@ -2822,8 +2822,8 @@ unit rgobj;
For non-x86 it is nevertheless possible to replace moves to/from the register For non-x86 it is nevertheless possible to replace moves to/from the register
with loads/stores to spilltemp (Sergei) } with loads/stores to spilltemp (Sergei) }
for counter := 0 to pred(regs.reginfocount) do for counter := 0 to pred(spregs.spillreginfocount) do
with regs.reginfo[counter] do with spregs.spillreginfo[counter] do
begin begin
if mustbespilled then if mustbespilled then
begin begin
@ -2891,12 +2891,12 @@ unit rgobj;
loadpos:=tai(loadpos.next); loadpos:=tai(loadpos.next);
{ Load the spilled registers } { Load the spilled registers }
for counter := 0 to pred(regs.reginfocount) do for counter := 0 to pred(spregs.spillreginfocount) do
with regs.reginfo[counter] do with spregs.spillreginfo[counter] do
begin begin
if mustbespilled and regread then if mustbespilled and regread then
begin begin
loadreg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints); loadreg:=getregisterinline(list,spregs.spillreginfo[counter].spillregconstraints);
do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],loadreg,orgreg); do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],loadreg,orgreg);
include(reginfo[getsupreg(loadreg)].flags,ri_spill_helper); include(reginfo[getsupreg(loadreg)].flags,ri_spill_helper);
end; end;
@ -2904,8 +2904,8 @@ unit rgobj;
{ Release temp registers of read-only registers, and add reference of the instruction { Release temp registers of read-only registers, and add reference of the instruction
to the reginfo } to the reginfo }
for counter := 0 to pred(regs.reginfocount) do for counter := 0 to pred(spregs.spillreginfocount) do
with regs.reginfo[counter] do with spregs.spillreginfo[counter] do
begin begin
if mustbespilled and regread and if mustbespilled and regread and
(ssa_safe or (ssa_safe or
@ -2926,8 +2926,8 @@ unit rgobj;
{ Allocate temp registers of write-only registers, and add reference of the instruction { Allocate temp registers of write-only registers, and add reference of the instruction
to the reginfo } to the reginfo }
for counter := 0 to pred(regs.reginfocount) do for counter := 0 to pred(spregs.spillreginfocount) do
with regs.reginfo[counter] do with spregs.spillreginfo[counter] do
begin begin
if mustbespilled and regwritten then if mustbespilled and regwritten then
begin begin
@ -2935,7 +2935,7 @@ unit rgobj;
if (not regread) or if (not regread) or
ssa_safe then ssa_safe then
begin begin
storereg:=getregisterinline(list,regs.reginfo[counter].spillregconstraints); storereg:=getregisterinline(list,spregs.spillreginfo[counter].spillregconstraints);
include(reginfo[getsupreg(storereg)].flags,ri_spill_helper); include(reginfo[getsupreg(storereg)].flags,ri_spill_helper);
{ we also use loadreg for store replacements in case we { we also use loadreg for store replacements in case we
don't have ensure ssa -> initialise loadreg even if don't have ensure ssa -> initialise loadreg even if
@ -2962,8 +2962,8 @@ unit rgobj;
if not assigned(instr.next) then if not assigned(instr.next) then
list.concat(tai_marker.Create(mark_Position)); list.concat(tai_marker.Create(mark_Position));
storepos:=tai(instr.next); storepos:=tai(instr.next);
for counter := 0 to pred(regs.reginfocount) do for counter := 0 to pred(spregs.spillreginfocount) do
with regs.reginfo[counter] do with spregs.spillreginfo[counter] do
begin begin
if mustbespilled and regwritten then if mustbespilled and regwritten then
begin begin
@ -2980,7 +2980,7 @@ unit rgobj;
{ substitute registers } { substitute registers }
for counter:=0 to instr.ops-1 do for counter:=0 to instr.ops-1 do
substitute_spilled_registers(regs,instr,counter); substitute_spilled_registers(spregs,instr,counter);
{ We have modified the instruction; perhaps the new instruction has { We have modified the instruction; perhaps the new instruction has
certain constraints regarding which imaginary registers interfere certain constraints regarding which imaginary registers interfere
with certain physical registers. } with certain physical registers. }