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* x86: Introduced TrySwapMovOp method, and redesigned TrySwapMovCmp
to use it while also trying to move one more instruction back
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
6af886c2b9
commit
5f3749dc49
@ -211,6 +211,7 @@ unit aoptx86;
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procedure ConvertJumpToRET(const p: tai; const ret_p: tai);
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function CheckJumpMovTransferOpt(var p: tai; hp1: tai; LoopCount: Integer; out Count: Integer): Boolean;
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function TrySwapMovOp(var p, hp1: tai): Boolean;
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function TrySwapMovCmp(var p, hp1: tai): Boolean;
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{ Processor-dependent reference optimisation }
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@ -8453,10 +8454,10 @@ unit aoptx86;
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Break;
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case taicpu(hp2).opcode of
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A_MOVSS:
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A_MOVSD:
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begin
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if taicpu(hp2).ops = 0 then
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{ Wrong MOVSS }
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{ Wrong MOVSD }
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Break;
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Inc(Count);
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if Count >= 5 then
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@ -8475,7 +8476,7 @@ unit aoptx86;
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A_MOVZX,
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A_MOVAPS,
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A_MOVUPS,
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A_MOVSD,
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A_MOVSS,
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A_MOVAPD,
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A_MOVUPD,
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A_MOVDQA,
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@ -8626,41 +8627,38 @@ unit aoptx86;
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end;
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function TX86AsmOptimizer.TrySwapMovCmp(var p, hp1: tai): Boolean;
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const
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WriteOp: array[0..3] of set of TInsChange = (
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[Ch_Wop1, Ch_RWop1, Ch_Mop1],
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[Ch_Wop2, Ch_RWop2, Ch_Mop2],
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[Ch_Wop3, Ch_RWop3, Ch_Mop3],
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[Ch_Wop4, Ch_RWop4, Ch_Mop4]);
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RegWriteFlags: array[0..7] of set of TInsChange = (
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{ The order is important: EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP }
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[Ch_WEAX, Ch_RWEAX, Ch_MEAX{$ifdef x86_64}, Ch_WRAX, Ch_RWRAX, Ch_MRAX{$endif x86_64}],
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[Ch_WECX, Ch_RWECX, Ch_MECX{$ifdef x86_64}, Ch_WRCX, Ch_RWRCX, Ch_MRCX{$endif x86_64}],
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[Ch_WEDX, Ch_RWEDX, Ch_MEDX{$ifdef x86_64}, Ch_WRDX, Ch_RWRDX, Ch_MRDX{$endif x86_64}],
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[Ch_WEBX, Ch_RWEBX, Ch_MEBX{$ifdef x86_64}, Ch_WRBX, Ch_RWRBX, Ch_MRBX{$endif x86_64}],
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[Ch_WESI, Ch_RWESI, Ch_MESI{$ifdef x86_64}, Ch_WRSI, Ch_RWRSI, Ch_MRSI{$endif x86_64}],
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[Ch_WEDI, Ch_RWEDI, Ch_MEDI{$ifdef x86_64}, Ch_WRDI, Ch_RWRDI, Ch_MRDI{$endif x86_64}],
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[Ch_WEBP, Ch_RWEBP, Ch_MEBP{$ifdef x86_64}, Ch_WRBP, Ch_RWRBP, Ch_MRBP{$endif x86_64}],
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[Ch_WESP, Ch_RWESP, Ch_MESP{$ifdef x86_64}, Ch_WRSP, Ch_RWRSP, Ch_MRSP{$endif x86_64}]);
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function TX86AsmOptimizer.TrySwapMovOp(var p, hp1: tai): Boolean;
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var
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hp2: tai;
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X: Integer;
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const
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WriteOp: array[0..3] of set of TInsChange = (
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[Ch_Wop1, Ch_RWop1, Ch_Mop1],
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[Ch_Wop2, Ch_RWop2, Ch_Mop2],
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[Ch_Wop3, Ch_RWop3, Ch_Mop3],
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[Ch_Wop4, Ch_RWop4, Ch_Mop4]);
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RegWriteFlags: array[0..7] of set of TInsChange = (
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{ The order is important: EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP }
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[Ch_WEAX, Ch_RWEAX, Ch_MEAX{$ifdef x86_64}, Ch_WRAX, Ch_RWRAX, Ch_MRAX{$endif x86_64}],
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[Ch_WECX, Ch_RWECX, Ch_MECX{$ifdef x86_64}, Ch_WRCX, Ch_RWRCX, Ch_MRCX{$endif x86_64}],
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[Ch_WEDX, Ch_RWEDX, Ch_MEDX{$ifdef x86_64}, Ch_WRDX, Ch_RWRDX, Ch_MRDX{$endif x86_64}],
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[Ch_WEBX, Ch_RWEBX, Ch_MEBX{$ifdef x86_64}, Ch_WRBX, Ch_RWRBX, Ch_MRBX{$endif x86_64}],
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[Ch_WESI, Ch_RWESI, Ch_MESI{$ifdef x86_64}, Ch_WRSI, Ch_RWRSI, Ch_MRSI{$endif x86_64}],
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[Ch_WEDI, Ch_RWEDI, Ch_MEDI{$ifdef x86_64}, Ch_WRDI, Ch_RWRDI, Ch_MRDI{$endif x86_64}],
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[Ch_WEBP, Ch_RWEBP, Ch_MEBP{$ifdef x86_64}, Ch_WRBP, Ch_RWRBP, Ch_MRBP{$endif x86_64}],
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[Ch_WESP, Ch_RWESP, Ch_MESP{$ifdef x86_64}, Ch_WRSP, Ch_RWRSP, Ch_MRSP{$endif x86_64}]);
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begin
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{ If we have something like:
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cmp ###,%reg1
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mov 0,%reg2
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op ###,###
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mov ###,###
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And no modified registers are shared, move the instruction to before
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the comparison as this means it can be optimised without worrying
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about the FLAGS register. (CMP/MOV is generated by
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"J(c)Mov1JmpMov0 -> Set(~c)", among other things).
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Try to move the MOV instruction to before OP as long as OP and MOV don't
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interfere in regards to what they write to.
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As long as the second instruction doesn't use the flags or one of the
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registers used by CMP or TEST (also check any references that use the
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registers), then it can be moved prior to the comparison.
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NOTE: p must be a 2-operand instruction
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}
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Result := False;
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@ -8672,12 +8670,12 @@ unit aoptx86;
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{ NOP is a pipeline fence, likely marking the beginning of the function
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epilogue, so drop out. Similarly, drop out if POP or RET are
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encountered }
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if MatchInstruction(hp1, A_NOP, A_POP, []) then
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if MatchInstruction(hp1, A_NOP, A_POP, A_RET, []) then
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Exit;
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if (taicpu(hp1).opcode = A_MOVSS) and
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if (taicpu(hp1).opcode = A_MOVSD) and
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(taicpu(hp1).ops = 0) then
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{ Wrong MOVSS }
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{ Wrong MOVSD }
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Exit;
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{ Check for writes to specific registers first }
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@ -8705,6 +8703,25 @@ unit aoptx86;
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Exit;
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end;
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{ Check p to make sure it doesn't write to something that affects hp1 }
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{ Check for writes to specific registers first }
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{ EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP in that order }
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for X := 0 to 7 do
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if (RegWriteFlags[X] * InsProp[taicpu(p).opcode].Ch <> [])
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and RegInInstruction(newreg(R_INTREGISTER, TSuperRegister(X), R_SUBWHOLE), hp1) then
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Exit;
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for X := 0 to taicpu(p).ops - 1 do
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begin
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{ Check to see if this operand writes to something }
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if ((WriteOp[X] * InsProp[taicpu(p).opcode].Ch) <> []) and
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{ And matches something in hp1 }
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(taicpu(p).oper[X]^.typ = top_reg) and
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RegInInstruction(taicpu(p).oper[X]^.reg, hp1) then
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Exit;
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end;
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{ The instruction can be safely moved }
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asml.Remove(hp1);
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@ -8712,6 +8729,17 @@ unit aoptx86;
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can be optimised into "xor %reg,%reg" later }
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if SetAndTest(FindRegAllocBackward(NR_DEFAULTFLAGS, tai(p.Previous)), hp2) then
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asml.InsertBefore(hp1, hp2)
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{ Failing that, try to insert after the last instructions where the
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FLAGS register is not yet in use }
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else if GetLastInstruction(p, hp2) and
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(
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(hp2.typ <> ait_instruction) or
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{ Don't insert after an instruction that uses the flags when p doesn't use them }
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RegInInstruction(NR_DEFAULTFLAGS, p) or
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not RegInInstruction(NR_DEFAULTFLAGS, hp2)
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) then
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asml.InsertAfter(hp1, hp2)
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else
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{ Note, if p.Previous is nil (even if it should logically never be the
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case), FindRegAllocBackward immediately exits with False and so we
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@ -8721,26 +8749,90 @@ unit aoptx86;
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DebugMsg(SPeepholeOptimization + 'Swapped ' + debug_op2str(taicpu(p).opcode) + ' and ' + debug_op2str(taicpu(hp1).opcode) + ' instructions to improve optimisation potential', hp1);
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{ We can't trust UsedRegs because we're looking backwards, although we
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know the registers are allocated after p at the very least, so manually
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create tai_regalloc objects if needed }
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for X := 0 to taicpu(hp1).ops - 1 do
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case taicpu(hp1).oper[X]^.typ of
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top_reg:
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AllocRegBetween(taicpu(hp1).oper[X]^.reg, hp1, p, UsedRegs);
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begin
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asml.InsertBefore(tai_regalloc.alloc(taicpu(hp1).oper[X]^.reg, nil), hp1);
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IncludeRegInUsedRegs(taicpu(hp1).oper[X]^.reg, UsedRegs);
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AllocRegBetween(taicpu(hp1).oper[X]^.reg, hp1, p, UsedRegs);
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end;
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top_ref:
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begin
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if taicpu(hp1).oper[X]^.ref^.base <> NR_NO then
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AllocRegBetween(taicpu(hp1).oper[X]^.ref^.base, hp1, p, UsedRegs);
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begin
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asml.InsertBefore(tai_regalloc.alloc(taicpu(hp1).oper[X]^.ref^.base, nil), hp1);
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IncludeRegInUsedRegs(taicpu(hp1).oper[X]^.ref^.base, UsedRegs);
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AllocRegBetween(taicpu(hp1).oper[X]^.ref^.base, hp1, p, UsedRegs);
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end;
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if taicpu(hp1).oper[X]^.ref^.index <> NR_NO then
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AllocRegBetween(taicpu(hp1).oper[X]^.ref^.index, hp1, p, UsedRegs);
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begin
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asml.InsertBefore(tai_regalloc.alloc(taicpu(hp1).oper[X]^.ref^.index, nil), hp1);
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IncludeRegInUsedRegs(taicpu(hp1).oper[X]^.ref^.index, UsedRegs);
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AllocRegBetween(taicpu(hp1).oper[X]^.ref^.index, hp1, p, UsedRegs);
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end;
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end;
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else
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;
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end;
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Result := True;
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end;
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function TX86AsmOptimizer.TrySwapMovCmp(var p, hp1: tai): Boolean;
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var
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hp2: tai;
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X: Integer;
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begin
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{ If we have something like:
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cmp ###,%reg1
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mov 0,%reg2
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And no modified registers are shared, move the instruction to before
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the comparison as this means it can be optimised without worrying
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about the FLAGS register. (CMP/MOV is generated by
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"J(c)Mov1JmpMov0 -> Set(~c)", among other things).
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As long as the second instruction doesn't use the flags or one of the
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registers used by CMP or TEST (also check any references that use the
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registers), then it can be moved prior to the comparison.
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}
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Result := False;
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if not TrySwapMovOp(p, hp1) then
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Exit;
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if taicpu(hp1).opcode = A_LEA then
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{ The flags will be overwritten by the CMP/TEST instruction }
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ConvertLEA(taicpu(hp1));
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Result := True;
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{ Can we move it one further back? }
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if GetLastInstruction(hp1, hp2) and (hp2.typ = ait_instruction) and
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{ Check to see if CMP/TEST is a comparison against zero }
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(
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(
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(taicpu(p).opcode = A_CMP) and
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MatchOperand(taicpu(p).oper[0]^, 0)
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) or
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(
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(taicpu(p).opcode = A_TEST) and
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(
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OpsEqual(taicpu(p).oper[0]^, taicpu(p).oper[1]^) or
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MatchOperand(taicpu(p).oper[0]^, -1)
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)
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)
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) and
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{ These instructions set the zero flag if the result is zero }
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MatchInstruction(hp2, [A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_POPCNT, A_LZCNT], []) and
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OpsEqual(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) then
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{ Looks like we can - if successful, this benefits PostPeepholeOptTestOr }
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TrySwapMovOp(hp2, hp1);
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end;
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