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+ patch by Jeppe Johansen to make use of the div/udiv instruction on arm7m, resolves #20022
* explicitly make symbol addressing PC relative git-svn-id: trunk@19221 -
This commit is contained in:
florian
parent
b0b12d3a64
commit
5fa184c952
@ -283,6 +283,7 @@ unit cgcpu;
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current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
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hr.symbol:=l;
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hr.base:=NR_PC;
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list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
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end;
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end;
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@ -640,8 +641,7 @@ unit cgcpu;
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if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
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case op of
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OP_NEG,OP_NOT,
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OP_DIV,OP_IDIV:
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OP_NEG,OP_NOT:
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internalerror(200308281);
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OP_SHL:
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begin
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@ -742,11 +742,11 @@ unit cgcpu;
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else
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begin
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{ there could be added some more sophisticated optimizations }
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if (op in [OP_MUL,OP_IMUL]) and (a=1) then
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if (op in [OP_MUL,OP_IMUL,OP_DIV,OP_IDIV]) and (a=1) then
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a_load_reg_reg(list,size,size,src,dst)
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else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
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a_load_const_reg(list,size,0,dst)
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else if (op in [OP_IMUL]) and (a=-1) then
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else if (op in [OP_IMUL,OP_IDIV]) and (a=-1) then
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a_op_reg_reg(list,OP_NEG,size,src,dst)
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{ we do this here instead in the peephole optimizer because
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it saves us a register }
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@ -3192,8 +3192,7 @@ unit cgcpu;
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begin
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ovloc.loc:=LOC_VOID;
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case op of
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OP_NEG,OP_NOT,
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OP_DIV,OP_IDIV:
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OP_NEG,OP_NOT:
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internalerror(200308281);
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OP_ROL:
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begin
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@ -54,7 +54,8 @@ implementation
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pass_2,procinfo,
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ncon,
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cpubase,cpuinfo,
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ncgutil,cgcpu;
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ncgutil,cgcpu,
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nadd,pass_1,symdef;
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{*****************************************************************************
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TARMMODDIVNODE
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@ -72,6 +73,26 @@ implementation
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) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else if (current_settings.cputype in [cpu_armv7m]) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else if (current_settings.cputype in [cpu_armv7m]) and
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(nodetype=modn) and
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not(is_64bitint(resultdef)) then
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begin
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if (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) and
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(tordconstnode(right).value<=256) and
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(tordconstnode(right).value>0) then
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result:=caddnode.create(andn,left,cordconstnode.create(tordconstnode(right).value-1,sinttype,false))
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else
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begin
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result:=caddnode.create(subn,left,caddnode.create(muln,right.getcopy, cmoddivnode.Create(divn,left.getcopy,right.getcopy)));
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right:=nil;
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end;
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left:=nil;
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end
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else
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result:=inherited first_moddivint;
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end;
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@ -167,37 +188,74 @@ implementation
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begin
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secondpass(left);
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secondpass(right);
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resultdef);
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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size,true);
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location_copy(location,left.location);
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numerator:=location.register;
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resultreg:=location.register;
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if location.loc=LOC_CREGISTER then
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if (current_settings.cputype in [cpu_armv7m]) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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begin
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size:=def_cgsize(left.resultdef);
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location_force_reg(current_asmdata.CurrAsmList,left.location,size,true);
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location_copy(location,left.location);
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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end
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else if (nodetype=modn) or (right.nodetype=ordconstn) then
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begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg:=cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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if right.nodetype=ordconstn then
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begin
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if nodetype=divn then
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genOrdConstNodeDiv
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if (right.nodetype=ordconstn) and
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((tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1)) or
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(tordconstnode(right).value=0) or
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ispowerof2(tordconstnode(right).value,power)) then
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begin
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numerator:=left.location.register;
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genOrdConstNodeDiv;
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end
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else
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// genOrdConstNodeMod;
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end;
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begin
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location_force_reg(current_asmdata.CurrAsmList,right.location,size,true);
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location.register:=resultreg;
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if is_signed(left.resultdef) or
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is_signed(right.resultdef) then
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_IDIV,OS_INT,right.location.register,left.location.register,location.register)
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else
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_DIV,OS_INT,right.location.register,left.location.register,location.register);
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end;
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end
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else
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begin
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resultdef);
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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size,true);
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location_copy(location,left.location);
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numerator:=location.register;
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resultreg:=location.register;
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if location.loc=LOC_CREGISTER then
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begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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end
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else if (nodetype=modn) or (right.nodetype=ordconstn) then
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begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg:=cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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if right.nodetype=ordconstn then
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begin
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if nodetype=divn then
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genOrdConstNodeDiv
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else
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// genOrdConstNodeMod;
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end;
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location.register:=resultreg;
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end;
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{ unsigned division/module can only overflow in case of division by zero }
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{ (but checking this overflow flag is more convoluted than performing a }
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@ -41,88 +41,9 @@
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function fpc_div_dword(n,z:dword):dword;[public,alias: 'FPC_DIV_DWORD'];assembler;nostackframe;
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asm
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{$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
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{$ifdef CPUCORTEXM3}
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udiv r0, r1, r0
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{$else}
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mov r3, #0
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rsbs r2, r0, r1, LSR#3
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bcc .Ldiv_3bits
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rsbs r2, r0, r1, LSR#8
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bcc .Ldiv_8bits
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mov r0, r0, LSL#8
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orr r3, r3, #0xFF000000
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rsbs r2, r0, r1, LSR#4
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bcc .Ldiv_4bits
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rsbs r2, r0, r1, LSR#8
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bcc .Ldiv_8bits
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mov r0, r0, LSL#8
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orr r3, r3, #0x00FF0000
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rsbs r2, r0, r1, LSR#8
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itt cs
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movcs r0, r0, LSL#8
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orrcs r3, r3, #0x0000FF00
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rsbs r2, r0, r1, LSR#4
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bcc .Ldiv_4bits
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rsbs r2, r0, #0
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bcs .Ldiv_by_0
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.Ldiv_loop:
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it cs
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movcs r0, r0, LSR#8
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.Ldiv_8bits:
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rsbs r2, r0, r1, LSR#7
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it cs
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subcs r1, r1, r0, LSL#7
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#6
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it cs
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subcs r1, r1, r0, LSL#6
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#5
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it cs
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subcs r1, r1, r0, LSL#5
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#4
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it cs
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subcs r1, r1, r0, LSL#4
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adc r3, r3, r3
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.Ldiv_4bits:
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rsbs r2, r0, r1, LSR#3
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it cs
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subcs r1, r1, r0, LSL#3
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adc r3, r3, r3
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.Ldiv_3bits:
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rsbs r2, r0, r1, LSR#2
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it cs
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subcs r1, r1, r0, LSL#2
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#1
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it cs
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subcs r1, r1, r0, LSL#1
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adc r3, r3, r3
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rsbs r2, r0, r1
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it cs
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subcs r1, r1, r0
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adcs r3, r3, r3
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.Ldiv_next:
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bcs .Ldiv_loop
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mov r0, r3
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{$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
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mov pc, lr
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{$if defined(CPUARMV7M)}
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udiv r0, r0, r1
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{$else}
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bx lr
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{$endif}
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.Ldiv_by_0:
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mov r0, #200
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mov r1, r11
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bl handleerrorframe
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{$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
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mov pc, lr
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{$else}
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bx lr
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{$endif}
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{$endif}
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{$else}
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mov r3, #0
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rsbs r2, r0, r1, LSR#3
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bcc .Ldiv_3bits
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@ -189,7 +110,7 @@ asm
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{$else}
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bx lr
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{$endif}
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{$endif}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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@ -201,26 +122,9 @@ function fpc_div_dword(n,z:dword):dword;external name 'FPC_DIV_DWORD';
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function fpc_div_longint(n,z:longint):longint;[public,alias: 'FPC_DIV_LONGINT'];assembler;nostackframe;
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asm
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{$if defined(CPUCORTEXM3) or defined(CPUARMV7M)}
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{$ifdef CPUCORTEXM3}
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sdiv r0, r1, r0
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{$else}
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stmfd sp!, {lr}
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ands r12, r0, #1<<31 (* r12:=r0 and $80000000 *)
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it mi
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rsbmi r0, r0, #0 (* if signed(r0) then r0:=0-r0 *)
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eors r12, r12, r1, ASR#32 (* r12:=r12 xor (r1 asr 32) *)
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it cs
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rsbcs r1, r1, #0 (* if signed(r12) then r1:=0-r1 *)
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bl fpc_div_dword
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movs r12, r12, LSL#1 (* carry:=sign(r12) *)
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it cs
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rsbcs r0, r0, #0
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it mi
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rsbmi r1, r1, #0
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ldmfd sp!, {pc}
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{$endif}
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{$else}
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{$if defined(CPUARMV7M)}
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sdiv r0, r0, r1
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{$else}
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stmfd sp!, {lr}
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ands r12, r0, #1<<31 (* r12:=r0 and $80000000 *)
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rsbmi r0, r0, #0 (* if signed(r0) then r0:=0-r0 *)
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@ -231,7 +135,7 @@ asm
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rsbcs r0, r0, #0
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rsbmi r1, r1, #0
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ldmfd sp!, {pc}
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{$endif}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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@ -243,10 +147,16 @@ function fpc_div_longint(n,z:longint):longint;external name 'FPC_DIV_LONGINT';
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function fpc_mod_dword(n,z:dword):dword;[public,alias: 'FPC_MOD_DWORD'];assembler;nostackframe;
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asm
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{$if defined(CPUARMV7M)}
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udiv r2, r0, r1
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mul r2,r1,r2
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sub r0,r0,r2
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{$else}
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stmfd sp!, {lr}
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bl fpc_div_dword
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mov r0, r1
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ldmfd sp!, {pc}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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@ -258,10 +168,16 @@ function fpc_mod_dword(n,z:dword):dword;external name 'FPC_MOD_DWORD';
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function fpc_mod_longint(n,z:longint):longint;[public,alias: 'FPC_MOD_LONGINT'];assembler;nostackframe;
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asm
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{$if defined(CPUARMV7M)}
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sdiv r2, r0, r1
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smull r2,r3,r1,r2
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sub r0,r0,r2
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{$else}
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stmfd sp!, {lr}
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bl fpc_div_longint
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mov r0, r1
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ldmfd sp!, {pc}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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