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* fixed compilation of AVR compiler
git-svn-id: trunk@13342 -
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@ -120,7 +120,6 @@ Const
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'AT91SAM7x256'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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@ -181,7 +181,7 @@ unit cgcpu;
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a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
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LOC_REFERENCE:
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begin
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reference_reset_base(ref,location^.reference.index,location^.reference.offset,araloc.alignment);
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reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
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{ doubles in softemu mode have a strange order of registers and references }
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if location^.size=OS_32 then
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g_concatcopy(list,tmpref,ref,4)
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@ -40,6 +40,16 @@ Type
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fp_libgcc
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);
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tcontrollertype =
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(ct_none,
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ct_atmega16,
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ct_atmega32,
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ct_atmega48,
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ct_atmega64,
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ct_atmega128
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);
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Const
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{# Size of native extended floating point type }
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extended_size = 12;
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@ -71,6 +81,23 @@ Const
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'LIBGCC'
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);
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controllertypestr : array[tcontrollertype] of string[20] =
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('',
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'ATMEGA16',
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'ATMEGA32',
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'ATMEGA48',
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'ATMEGA64',
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'ATMEGA128'
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);
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controllerunitstr : array[tcontrollertype] of string[20] =
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('',
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'ATMEGA16',
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'ATMEGA32',
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'ATMEGA48',
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'ATMEGA64',
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'ATMEGA128'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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@ -123,8 +123,8 @@ implementation
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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{
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begin
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{
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end
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@ -138,9 +138,9 @@ interface
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disabledircache : boolean;
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{ CPU targets with microcontroller support can add a controller specific unit }
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{$if defined(ARM)}
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{$if defined(ARM) or defined(AVR)}
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controllertype : tcontrollertype;
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{$endif defined(ARM)}
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{$endif defined(ARM) or defined(AVR)}
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end;
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const
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