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minor bugfixes avx512 tests

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git-svn-id: branches/tg74/avx512@39740 -
This commit is contained in:
tg74 2018-09-12 05:03:05 +00:00
parent c894768a65
commit 608992ecf5
8 changed files with 133 additions and 32 deletions
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2
compiler/i386/i386nop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from x86ins.dat }
4047;
4048;

7
compiler/i386/i386tab.inc
View File

@ -19880,6 +19880,13 @@
code : #232#234#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;
optypes : (ot_xmmreg_mz,ot_xmmreg,ot_xmmreg_er,ot_none);
code : #232#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;

2
compiler/i8086/i8086nop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from x86ins.dat }
4079;
4080;

7
compiler/i8086/i8086tab.inc
View File

@ -20104,6 +20104,13 @@
code : #232#234#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;
optypes : (ot_xmmreg_mz,ot_xmmreg,ot_xmmreg_er,ot_none);
code : #232#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;

2
compiler/x86_64/x8664nop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from x86ins.dat }
4100;
4101;

7
compiler/x86_64/x8664tab.inc
View File

@ -20251,6 +20251,13 @@
code : #232#234#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;
optypes : (ot_xmmreg_mz,ot_xmmreg,ot_xmmreg_er,ot_none);
code : #232#241#249#1#189#72;
flags : [if_avx512]
),
(
opcode : A_VFNMADD231SS;
ops : 3;

129
tests/utils/avx/asmtestgenerator.pas
View File

@ -85,7 +85,7 @@ type
FSAE: boolean;
procedure MemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList);
procedure VectorMemRegBaseIndexCombi(const aPrefix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList);
procedure VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList);
function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList;
public
@ -537,7 +537,7 @@ begin
//TG TODO delete
if aInst = 'valignd' then
if aInst = 'vpmovw2m' then
begin
sSuffix := sSuffix;
end;
@ -1237,7 +1237,8 @@ begin
Item.Values.Add('0');
end
else if AnsiSameText(sl_Operand, 'XMEM32') then
else if AnsiSameText(sl_Operand, 'XMEM32') or
AnsiSameText(sl_Operand, 'XMEM32_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otXMEM32;
@ -1245,33 +1246,51 @@ begin
if UsePrefix then sl_Prefix := 'oword ';
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, 'XMEM64') then
else if AnsiSameText(sl_Operand, 'XMEM64') or
AnsiSameText(sl_Operand, 'XMEM64_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otXMEM64;
Item.OpActive := true;
if UsePrefix then sl_Prefix := 'oword ';
//if UsePrefix then sl_Prefix := 'oword ';
//
//if x64 then
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values);
//end
//else
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values);
//end;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64XMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32XMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, 'YMEM32') then
else if AnsiSameText(sl_Operand, 'YMEM32') or
AnsiSameText(sl_Operand, 'YMEM32_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otYMEM32;
@ -1279,16 +1298,30 @@ begin
if UsePrefix then sl_Prefix := 'yword ';
//if x64 then
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
//end
//else
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
//end;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, 'YMEM64') then
else if AnsiSameText(sl_Operand, 'YMEM64') or
AnsiSameText(sl_Operand, 'YMEM64_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otYMEM64;
@ -1296,16 +1329,30 @@ begin
if UsePrefix then sl_Prefix := 'yword ';
//if x64 then
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
//end
//else
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
//end;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64YMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32YMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, 'ZMEM32') then
else if AnsiSameText(sl_Operand, 'ZMEM32') or
AnsiSameText(sl_Operand, 'ZMEM32_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otZMEM32;
@ -1313,16 +1360,30 @@ begin
if UsePrefix then sl_Prefix := 'zword ';
//if x64 then
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values);
//end
//else
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values);
//end;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, 'ZMEM64') then
else if AnsiSameText(sl_Operand, 'ZMEM64') or
AnsiSameText(sl_Operand, 'ZMEM64_M') then
begin
Item.OpNumber := il_Op;
Item.OpTyp := otZMEM64;
@ -1330,14 +1391,27 @@ begin
if UsePrefix then sl_Prefix := 'zword ';
//if x64 then
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values);
//end
//else
//begin
// VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values);
//end;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if x64 then
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64ZMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg64Base, FReg64ZMMIndex, Item.Values);
end
else
begin
VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32ZMMIndex, Item.Values);
VectorMemRegBaseIndexCombi(sl_prefix, sSuffix, FReg32Base, FReg32ZMMIndex, Item.Values);
end;
end
else if AnsiSameText(sl_Operand, '2B32') then
begin
@ -1458,6 +1532,7 @@ begin
Item.OpTyp := otKREG;
Item.OpActive := true;
sSuffix := '';
if Pos('_M', AnsiUppercase(sl_Operand)) > 0 then sSuffix := ' {k1}';
if UsePrefix then sl_Prefix := '';
@ -1911,7 +1986,7 @@ begin
end;
end;
procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix: String;
procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix, aSuffix: String;
aSLBaseReg, aSLIndexReg, aRList: TStringList);
var
il_Base: integer;
@ -1938,18 +2013,18 @@ begin
for il_Index := 0 to aSLIndexReg.Count - 1 do
begin
aRList.Add(format(aPrefix + '[%s + %s]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix]));
aRList.Add(format(aPrefix + '[%s + %s * 2]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
aRList.Add(format(aPrefix + '[%s + %s * 4]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
aRList.Add(format(aPrefix + '[%s + %s * 8]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
aRList.Add(format(aPrefix + '[%s + %s * 2]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix]));
aRList.Add(format(aPrefix + '[%s + %s * 4]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix]));
aRList.Add(format(aPrefix + '[%s + %s * 8]%s', [aSLBaseReg[il_Base], aSLIndexReg[il_Index], aSuffix]));
//aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
//aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
//aRList.Add(format(aPrefix + '[%s + %s * 8 + 48]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
aRList.Add(format(aPrefix + '[%s + %s]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]]));
aRList.Add(format(aPrefix + '[%s + %s]%s', [aSLIndexReg[il_Index], aSLBaseReg[il_Base], aSuffix]));
//aRList.Add(format(aPrefix + '[%s + %s + 16]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]]));
end;

9
tests/webtbs/tw13294.pp
View File

@ -1,6 +1,7 @@
{ %skiptarget=android }
{ %cpu=i386,x86_64 }
{ %opt=-Cg- }
{$asmmode intel}
program movdtest;
var
@ -12,8 +13,12 @@ begin
movd a, %xmm0
movd %xmm0, b
{$else}
movd a(%rip), %xmm0
movd %xmm0, b(%rip)
// movd a(%rip), %xmm0
// movd %xmm0, b(%rip)
movd xmm0, a[rip]
movd b[rip], xmm0
{$endif}
end;
if b<>128133443 then