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* x86: Improvement to CMP/JE/CMP/@Lbl/SETE ->
CMP/SETE/CMP/SETE/OR optimisation to reduce pass counts (and work better with improved FLAGS register allocation).
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@ -6829,52 +6829,71 @@ unit aoptx86;
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{ The first operand of CMP instructions can only be a register or
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immediate anyway, so no need to check }
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GetNextInstruction(hp2, p_label) and
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(p_label.typ = ait_label) and
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(
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(p_label.typ = ait_label) or
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(
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{ Sometimes there's a zero-distance jump before the label, so deal with it here
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to potentially cut down on the iterations of Pass 1 }
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MatchInstruction(p_label, A_Jcc, []) and
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IsJumpToLabel(taicpu(p_label)) and
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{ Use p_dist to hold the jump briefly }
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SetAndTest(p_label, p_dist) and
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GetNextInstruction(p_dist, p_label) and
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(p_label.typ = ait_label) and
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(tai_label(p_label).labsym.getrefs >= 2) and
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(JumpTargetOp(taicpu(p_dist))^.ref^.symbol = tai_label(p_label).labsym) and
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{ We might as well collapse the jump now }
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CollapseZeroDistJump(p_dist, tai_label(p_label).labsym)
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)
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) and
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(tai_label(p_label).labsym.getrefs = 1) and
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(JumpTargetOp(taicpu(hp1))^.ref^.symbol = tai_label(p_label).labsym) and
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GetNextInstruction(p_label, p_dist) and
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MatchInstruction(p_dist, A_SETcc, []) and
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(taicpu(p_dist).condition in [C_E, C_Z]) and
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(taicpu(p_dist).oper[0]^.typ = top_reg) then
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(taicpu(p_dist).oper[0]^.typ = top_reg) and
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{ Get the instruction after the SETcc instruction so we can
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allocate a new register over the entire range }
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GetNextInstruction(p_dist, hp1_dist) then
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(p_label.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(p_dist.Next));
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// UpdateUsedRegs(TmpUsedRegs, tai(p_dist.Next));
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if not RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) and
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{ Get the instruction after the SETcc instruction so we can
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allocate a new register over the entire range }
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GetNextInstruction(p_dist, hp1_dist) then
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{ Register can appear in p if it's not used afterwards, so only
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allocate between hp1 and hp1_dist }
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NewReg := GetIntRegisterBetween(R_SUBL, TmpUsedRegs, hp1, hp1_dist);
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if (NewReg <> NR_NO) and
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{ RegUsedAfterInstruction modifies TmpUsedRegs }
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not RegUsedAfterInstruction(NR_DEFAULTFLAGS, p_dist, TmpUsedRegs) then
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begin
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{ Register can appear in p if it's not used afterwards, so only
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allocate between hp1 and hp1_dist }
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NewReg := GetIntRegisterBetween(R_SUBL, TmpUsedRegs, hp1, hp1_dist);
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if NewReg <> NR_NO then
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begin
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DebugMsg(SPeepholeOptimization + 'CMP/JE/CMP/@Lbl/SETE -> CMP/SETE/CMP/SETE/OR, removing conditional branch', p);
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DebugMsg(SPeepholeOptimization + 'CMP/JE/CMP/@Lbl/SETE -> CMP/SETE/CMP/SETE/OR, removing conditional branch', p);
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{ Change the jump instruction into a SETcc instruction }
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taicpu(hp1).opcode := A_SETcc;
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taicpu(hp1).opsize := S_B;
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taicpu(hp1).loadreg(0, NewReg);
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{ Change the jump instruction into a SETcc instruction }
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taicpu(hp1).opcode := A_SETcc;
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taicpu(hp1).opsize := S_B;
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taicpu(hp1).loadreg(0, NewReg);
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{ This is now a dead label }
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tai_label(p_label).labsym.decrefs;
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{ This is now a dead label }
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tai_label(p_label).labsym.decrefs;
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{ Prefer adding before the next instruction so the FLAGS
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register is deallicated first }
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AsmL.InsertBefore(
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taicpu.op_reg_reg(A_OR, S_B, NewReg, taicpu(p_dist).oper[0]^.reg),
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hp1_dist
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);
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hp2 := taicpu.op_reg_reg(A_OR, S_B, NewReg, taicpu(p_dist).oper[0]^.reg);
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Result := True;
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{ Don't exit yet, as p wasn't changed and hp1, while
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modified, is still intact and might be optimised by the
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SETcc optimisation below }
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end;
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{ Try to add the instruction right after the flags get deallocated, since
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the flags may become allocated again before the next instruction
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(reuse p_dist, not hp1, since that needs to remain as the
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instruction immediately after p) }
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if SetAndTest(FindRegDealloc(NR_DEFAULTFLAGS, tai(p_dist.Next)), p_dist) then
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AsmL.InsertAfter(hp2, p_dist)
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else
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AsmL.InsertBefore(hp2, hp1_dist);
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Result := True;
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{ Don't exit yet, as p wasn't changed and hp1, while
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modified, is still intact and might be optimised by the
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SETcc optimisation below }
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end;
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end;
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