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+ take advantage of the mla instruction when calculating array offsets
git-svn-id: trunk@21375 -
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@ -62,6 +62,7 @@ compiler/arm/narmcnv.pas svneol=native#text/plain
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compiler/arm/narmcon.pas svneol=native#text/plain
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compiler/arm/narmcon.pas svneol=native#text/plain
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compiler/arm/narminl.pas svneol=native#text/plain
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compiler/arm/narminl.pas svneol=native#text/plain
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compiler/arm/narmmat.pas svneol=native#text/plain
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compiler/arm/narmmat.pas svneol=native#text/plain
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compiler/arm/narmmem.pas svneol=native#text/plain
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compiler/arm/narmset.pas svneol=native#text/plain
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compiler/arm/narmset.pas svneol=native#text/plain
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compiler/arm/pp.lpi.template svneol=native#text/plain
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compiler/arm/pp.lpi.template svneol=native#text/plain
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compiler/arm/raarm.pas svneol=native#text/plain
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compiler/arm/raarm.pas svneol=native#text/plain
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@ -40,7 +40,8 @@ unit cpunode;
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narminl,
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narminl,
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narmcnv,
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narmcnv,
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narmcon,
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narmcon,
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narmset
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narmset,
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narmmem
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;
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;
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91
compiler/arm/narmmem.pas
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91
compiler/arm/narmmem.pas
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@ -0,0 +1,91 @@
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{
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Copyright (c) 2012 by Florian Klaempfl
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Generate arm assembler for in memory related nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmmem;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,
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cgbase,cpuinfo,cpubase,
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node,nmem,ncgmem;
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type
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tarmvecnode = class(tcgvecnode)
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procedure update_reference_reg_mul(maybe_const_reg: tregister; l: aint);override;
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end;
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implementation
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uses
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systems,
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cutils,verbose,
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symdef,paramgr,
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aasmtai,aasmdata,aasmcpu,
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nld,ncon,nadd,
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cgutils,cgobj;
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{*****************************************************************************
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TARMVECNODE
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*****************************************************************************}
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procedure tarmvecnode.update_reference_reg_mul(maybe_const_reg:tregister;l:aint);
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var
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hreg: tregister;
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hl : longint;
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begin
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if ((location.reference.base=NR_NO) and (location.reference.index=NR_NO)) or
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{ simple constant? }
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(l=1) or ispowerof2(l,hl) or ispowerof2(l+1,hl) or ispowerof2(l-1,hl) then
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inherited update_reference_reg_mul(maybe_const_reg,l)
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else if (location.reference.base<>NR_NO) then
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_ADDR,l,hreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MLA,hreg,maybe_const_reg,hreg,location.reference.base));
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location.reference.base:=hreg;
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{ update alignment }
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if (location.reference.alignment=0) then
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internalerror(2012052202);
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location.reference.alignment:=newalignment(location.reference.alignment,l);
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end
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else if (location.reference.index<>NR_NO) then
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begin
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_ADDR,l,hreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MLA,hreg,maybe_const_reg,hreg,location.reference.index));
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location.reference.base:=hreg;
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location.reference.index:=NR_NO;
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{ update alignment }
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if (location.reference.alignment=0) then
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internalerror(2012052203);
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location.reference.alignment:=newalignment(location.reference.alignment,l);
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end
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else
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internalerror(2012052201);
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end;
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begin
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cvecnode:=tarmvecnode;
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end.
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