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* SPARC: removed 32 bit shift code, and adjusted 64-bit shifts to take advantage of 3-address instructions (a port of r26142 for MIPS)
git-svn-id: trunk@26263 -
This commit is contained in:
sergei
parent
58cc531dd9
commit
6469d41e2a
@ -33,8 +33,8 @@ interface
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procedure pass_generate_code;override;
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end;
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tSparcshlshrnode = class(tshlshrnode)
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procedure pass_generate_code;override;
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tSparcshlshrnode = class(tcgshlshrnode)
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procedure second_64bit;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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@ -183,103 +183,66 @@ implementation
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end;
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procedure tSparcshlshrnode.pass_generate_code;
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procedure tSparcshlshrnode.second_64bit;
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var
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hregister,resultreg,hregister1,
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hreg64hi,hreg64lo : tregister;
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hregister,hreg64hi,hreg64lo : tregister;
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op : topcg;
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shiftval: aword;
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const
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ops: array [boolean] of topcg = (OP_SHR,OP_SHL);
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begin
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{ 64bit without constants need a helper, and is
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already replaced in pass1 }
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if is_64bit(left.resultdef) and
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(right.nodetype<>ordconstn) then
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if (right.nodetype<>ordconstn) then
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internalerror(200405301);
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secondpass(left);
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secondpass(right);
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if is_64bit(left.resultdef) then
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location_reset(location, LOC_REGISTER, def_cgsize(resultdef));
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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shiftval := tordconstnode(right).value.svalue and 63;
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op := ops[nodetype=shln];
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if shiftval > 31 then
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begin
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,u64inttype,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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shiftval := tordconstnode(right).value.svalue and 63;
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if shiftval > 31 then
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if nodetype = shln then
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begin
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if nodetype = shln then
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64hi);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval and 31,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64lo);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval and 31,hreg64hi,hreg64hi);
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end;
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location.register64.reglo:=hreg64hi;
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reglo);
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location.register64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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{ if shiftval and 31 = 0, it will optimize to MOVE }
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval and 31, hreg64lo, location.register64.reghi);
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end
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else
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begin
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{ shr 0 or shl 0 are noops, but generate wrong code below,
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so only add code if shift val is non-zero }
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if (shiftval <> 0) then
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begin
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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if nodetype = shln then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,32-shiftval,hreg64lo,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64hi,hreg64hi);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64hi,hreg64hi);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,32-shiftval,hreg64hi,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64lo,hreg64lo);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64lo,hreg64lo);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64hi,hreg64hi);
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end;
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end;
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location.register64.reghi:=hreg64hi;
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reghi);
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location.register64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval and 31, hreg64hi, location.register64.reglo);
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end;
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end
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else
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begin
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{ load left operators in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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location_copy(location,left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER) then
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location.register64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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location.register64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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hregister := cg.getintregister(current_asmdata.CurrAsmList, OS_32);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, shiftval, hreg64hi, location.register64.reghi);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, shiftval, hreg64lo, location.register64.reglo);
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if shiftval <> 0 then
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begin
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location.loc := LOC_REGISTER;
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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else
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op:=OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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if tordconstnode(right).value and 31<>0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,OS_32,tordconstnode(right).value.svalue and 31,hregister1,resultreg)
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end
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else
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begin
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{ load shift count in a register if necessary }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,OS_32,right.location.register,hregister1,resultreg);
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if nodetype = shln then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, 32-shiftval, hreg64lo, hregister);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, location.register64.reghi, location.register64.reghi);
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end
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else
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, 32-shiftval, hreg64hi, hregister);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, location.register64.reglo, location.register64.reglo);
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end;
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end;
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end;
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end;
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