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* patch by Nico Erfurth: Better support for PLD on ARM
git-svn-id: trunk@21572 -
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3db61ae52d
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@ -66,6 +66,7 @@ Implementation
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result:=
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result:=
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(p.typ=ait_instruction) and
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(p.typ=ait_instruction) and
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(taicpu(p).condition=C_None) and
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(taicpu(p).condition=C_None) and
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(taicpu(p).opcode<>A_PLD) and
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((taicpu(p).opcode<>A_BLX) or
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((taicpu(p).opcode<>A_BLX) or
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(taicpu(p).oper[0]^.typ=top_reg));
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(taicpu(p).oper[0]^.typ=top_reg));
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end;
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end;
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@ -140,7 +141,7 @@ Implementation
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case p.opcode of
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case p.opcode of
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{ These operands do not write into a register at all }
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{ These operands do not write into a register at all }
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A_CMP, A_CMN, A_TST, A_TEQ, A_B, A_BL, A_BX, A_BLX, A_SWI, A_MSR:
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A_CMP, A_CMN, A_TST, A_TEQ, A_B, A_BL, A_BX, A_BLX, A_SWI, A_MSR, A_PLD:
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exit;
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exit;
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{Take care of post/preincremented store and loads, they will change their base register}
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{Take care of post/preincremented store and loads, they will change their base register}
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A_STR, A_LDR:
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A_STR, A_LDR:
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@ -193,8 +194,9 @@ Implementation
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i:=1;
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i:=1;
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{For these instructions we have to start on oper[0]}
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{For these instructions we have to start on oper[0]}
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if (p.opcode in [A_STR, A_CMP, A_CMN, A_TST, A_TEQ,
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if (p.opcode in [A_STR, A_LDM, A_STM, A_PLD,
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A_B, A_BL, A_BX, A_BLX, A_LDM,
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A_CMP, A_CMN, A_TST, A_TEQ,
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A_B, A_BL, A_BX, A_BLX,
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A_SMLAL, A_UMLAL]) then i:=0;
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A_SMLAL, A_UMLAL]) then i:=0;
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while(i<p.ops) do
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while(i<p.ops) do
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