From 6529307d9ea60b90fd80b4a0ef430dcea3d0eafc Mon Sep 17 00:00:00 2001 From: masta Date: Tue, 7 Aug 2012 06:46:45 +0000 Subject: [PATCH] Don't emit useless AND/BICs in ARM CG In certain cases the CG would emit something like bic r1, r0, #0 As BIC is clearing the specified bits this is equivalent to mov r1, r0 This patch changes the CG to emit the mov instead which the register allocator will hopefully remove most of the time. git-svn-id: trunk@22024 - --- compiler/arm/cgcpu.pas | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas index 0d25017baa..4725ff372c 100644 --- a/compiler/arm/cgcpu.pas +++ b/compiler/arm/cgcpu.pas @@ -765,6 +765,8 @@ unit cgcpu; end { BIC clears the specified bits, while AND keeps them, using BIC allows to use a broader range of shifterconstants.} + else if (op = OP_AND) and (not(dword(a))=0) then + list.concat(taicpu.op_reg_reg(A_MOV,dst,src)) else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a)))) else if (op = OP_AND) and split_into_shifter_const(not(dword(a)), imm1, imm2) then