* fix assembling with official binutils

* fix compilation on 32 bit hosts
+ compile with -Sew

git-svn-id: branches/laksen/riscv_new@39482 -
This commit is contained in:
florian 2018-07-22 13:10:24 +00:00
parent 054bf32f1f
commit 65a415c13e
3 changed files with 13 additions and 13 deletions

View File

@ -23,9 +23,6 @@
<ExcludeFileFilter Value="*.(bak|ppu|ppw|o|so);*~;backup"/> <ExcludeFileFilter Value="*.(bak|ppu|ppw|o|so);*~;backup"/>
</PublishOptions> </PublishOptions>
<RunParams> <RunParams>
<local>
<LaunchingApplication PathPlusParams="\usr\X11R6\bin\xterm -T 'Lazarus Run Output' -e $(LazarusDir)\tools\runwait.sh $(TargetCmdLine)"/>
</local>
<FormatVersion Value="2"/> <FormatVersion Value="2"/>
<Modes Count="1"> <Modes Count="1">
<Mode0 Name="default"> <Mode0 Name="default">
@ -74,7 +71,8 @@
<ConfigFile> <ConfigFile>
<StopAfterErrCount Value="50"/> <StopAfterErrCount Value="50"/>
</ConfigFile> </ConfigFile>
<CustomOptions Value="-driscv64"/> <CustomOptions Value="-driscv64
-Sew"/>
</Other> </Other>
</CompilerOptions> </CompilerOptions>
</CONFIG> </CONFIG>

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@ -566,13 +566,15 @@ implementation
if Count > 0 then if Count > 0 then
begin begin
tmpreg1 := GetIntRegister(list, OS_INT); tmpreg1 := GetIntRegister(list, OS_INT);
for count2 := 1 to Count do count2 := 1;
begin while count2 <= Count do
list.concat(taicpu.op_reg_ref(A_LD, tmpreg1, src)); begin
list.concat(taicpu.op_reg_ref(A_SD, tmpreg1, dst)); list.concat(taicpu.op_reg_ref(A_LD, tmpreg1, src));
Inc(src.offset, 8); list.concat(taicpu.op_reg_ref(A_SD, tmpreg1, dst));
Inc(dst.offset, 8); Inc(src.offset, 8);
end; Inc(dst.offset, 8);
Inc(count2);
end;
len := len mod 8; len := len mod 8;
end; end;
if (len and 4) <> 0 then if (len and 4) <> 0 then

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@ -50,9 +50,9 @@ _start:
1:auipc gp, %pcrel_hi(__global_pointer$) 1:auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b) addi gp, gp, %pcrel_lo(1b)
.option pop .option pop
/* Clear the frame pointer since this is the outermost frame. */ /* Clear the frame pointer since this is the outermost frame. */
addi fp, x0, 0 addi x8, x0, 0
ld a2, 0(sp) ld a2, 0(sp)
addi sp, sp, 8 addi sp, sp, 8