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m68k: reinstate the inc/dec tempregister type hack again in an isolated way (it was removed in r40385, as it was breaking llvm target)

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git-svn-id: trunk@40453 -
This commit is contained in:
Károly Balogh 2018-12-02 18:54:04 +00:00
parent b9905f6a2c
commit 6629e72d79
2 changed files with 26 additions and 5 deletions
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16
compiler/m68k/n68kinl.pas
View File

@ -26,7 +26,7 @@ unit n68kinl;
interface
uses
node,ninl,ncginl,cpubase;
node,ninl,ncginl,symtype,cpubase;
type
t68kinlinenode = class(tcgInlineNode)
@ -51,6 +51,8 @@ interface
procedure second_frac_real; override;
{procedure second_prefetch; override;
procedure second_abs_long; override;}
protected
function second_incdec_tempregdef: tdef; override;
private
procedure second_do_operation(op: TAsmOp);
end;
@ -342,6 +344,18 @@ implementation
eor.l d1,d2
sub.l d1,d2
}
function t68kinlinenode.second_incdec_tempregdef: tdef;
begin
{ this kludge results in the increment/decrement value of inc/dec to be loaded
always in a datareg, regardless of the target type. This results in significantly
better code on m68k, where if the inc/decrement is loaded to an address register
for pointers, the compiler will generate a bunch of useless data<->address register
shuffling, as it cannot do some operations on address registers (like shifting
or multiplication) (KB) }
second_incdec_tempregdef:=cgsize_orddef(def_cgsize(left.resultdef));
end;
begin
cinlinenode:=t68kinlinenode;
end.

15
compiler/ncginl.pas
View File

@ -26,7 +26,7 @@ unit ncginl;
interface
uses
node,ninl;
node,ninl,symtype;
type
tcginlinenode = class(tinlinenode)
@ -66,6 +66,8 @@ interface
procedure second_seg; virtual; abstract;
procedure second_fma; virtual;
procedure second_frac_real; virtual;
protected
function second_incdec_tempregdef: tdef;virtual;
end;
implementation
@ -73,7 +75,7 @@ implementation
uses
globtype,constexp,
verbose,globals,compinnr,
symconst,symtype,symdef,defutil,
symconst,symdef,defutil,
aasmbase,aasmdata,
cgbase,pass_2,
cpubase,procinfo,
@ -332,6 +334,11 @@ implementation
{*****************************************************************************
INC/DEC GENERIC HANDLING
*****************************************************************************}
function tcginlinenode.second_incdec_tempregdef: tdef;
begin
second_incdec_tempregdef:=left.resultdef;
end;
procedure tcginlinenode.second_IncDec;
const
addsubop:array[in_inc_x..in_dec_x] of TOpCG=(OP_ADD,OP_SUB);
@ -382,7 +389,7 @@ implementation
addvalue:=addvalue*tpointerconstnode(tcallparanode(tcallparanode(left).right).left).value
else
begin
hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,tcallparanode(tcallparanode(left).right).left.resultdef,left.resultdef,addvalue<=1);
hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,tcallparanode(tcallparanode(left).right).left.resultdef,second_incdec_tempregdef,addvalue<=1);
hregister:=tcallparanode(tcallparanode(left).right).left.location.register;
{$ifndef cpu64bitalu}
hregisterhi:=tcallparanode(tcallparanode(left).right).left.location.register64.reghi;
@ -684,7 +691,7 @@ implementation
tempreg1:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
tempreg2:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,left.resultdef,left.resultdef.size*8-1,left.location.register,tempreg1);
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,left.location.register,tempreg1,tempreg2);
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmlist,OP_SUB,left.resultdef,tempreg1,tempreg2,location.register);